1. Beyond Si MOSFETs
Part IV

2. Alternative Transistor Structures
Silicon-on -insulator (SOI) technology
Multistage transistor

3. CMOS scaling bottleneck
Sub threshold slope
Gate leakage
Increase of off-state leakage currents with decreasing threshold voltage
Increase of gate leakage currents due to tunneling effects
Increase of sub-threshold slope as doping density in channel cannot be increased without paying in mobility

4. Double gate FETs Single gating Double gating
Increases control of the gate(s) on the channel
2nd gate shields drain
2nd gate allows DT mode
Higher current drive

5. Double gate FETs
Capacitive coupling
Single gating
Double gating

6. Advantages double gating
Reduction of DIBL
Improved sub-threshold slope S

7. Why Multi-Gate SOI MOSFETs?
Higher current drift (better performance).
Prophesized to show higher tolerance to scaling.
Better integration feasibility, raised source-drain structure, ease in integration.
Larger number of parameters to tailor device performance.

8. Double Gate FETs Control of VT
Via doping of the substrate, however in very small devices in-homogeneity local number/”nano-scopic” volume
Undoped substrate, using metal gates
- Choice of workfunctions larger than with n or p-doped polySi
Asymmetric gates
- Workfunction of the two gates different:
-Top gate: channel inversion
-Bottom gate : bulk control
- 1 channel
Symmetric gates
- Workfunction of the two gates same:
-Top gate : channel inversion
-Bottom gate: channel inversion
- 2 channels- possibly interacting

9. Double gate FETs
Energy bands- same voltage on both gates

10. Double gate FETs Cfr. a-symmetric gate
Energy bands- different voltages on both gates
Cfr. a-symmetric gate
Voltage on the 2nd gate influences the threshold voltage of the first gate.
2nd gate controls the value of the threshold voltage.
2nd gate can shift VT to required value

11. Double gate FETs Gate alignment
Problems that have hindered progress of the DGFET approach are:
Alignment issues:
Definition of both gates to the same image size accurately.
Self alignment of the source/drain regions to both top and bottom gates.
Alignment of the two gates to one another.
Connecting two gates with a low-resistance path.
These are needed for high current drive and low capacitances.
Circuit design issue:
Area efficient means needs to be designed to connect the two gates together.

13. Layout of Double Gate Type I : Planar Double Gate
Type II : Vertical Double Gate
Type III : Horizontal Double Gate (FinFET)

14. Problems: alignments of gates Contacting gates.
3 DG-FET Structures
Problems: alignments of gates
Contacting gates.

15. 3 DG-FET structures

16. 3 DG-FET structures

17. FET parameters defined by lithography
Type
S-D direction
Gate to gate direction
Gate length control (L)
Channel thickness control (W)
Top area I
In plane
Perpendicular to plane
Litho/etch
Planar layer
LxW II
WxH
Litho etch
LxH

18. And the winner is…finFETs
No gate alignment problems.
Independent gate control possible.
CMOS compatible processing ‘’trick’’ using side wall spacer technology to define the fin but not straightforward.

19. Solutions for the Short Channel Effect (SCE)
Non-classical FET structures
Devices
SOI
Band engineered FET
Double gate FET
Concept
Fully depleted channel on oxide
MODFET/strained Si channels
Vertical FETs/gate surround or two gates
Advantages
S, VT control
Ion , fT
Ion , S, SCE
Scaling issues
Si thickness, SCE
BC,QW thickness
Processing complexity, Si thickness, QM effects