© 2010 Altera Corporation—Public Easily Build Designs Using Altera’s Video and Image Processing Framework 2010 Technology Roadshow

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Agenda What is the video framework? Six steps to building a video system Video design demo using SOPC Builder Summary 2

© 2010 Altera Corporation—Public Altera Video Design Framework

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Altera Video Design Framework Higher Designer Productivity = Faster Time to Market 4

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Video IP Building Blocks: IPS-Video ‘Interlacer’ core in v10.1 5

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Open, Low-Overhead, Interface Standard: Avalon Streaming (ST) Video Open Interface Protocol for Streaming Video Datapaths and Memory-Mapped Control Paths 6

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Portfolio of Reference Designs 7

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Video Development Kits Cyclone III FPGA, $1,895 Stratix IV FPGA, $4,995 Cyclone III FPGA, $2,995 Arria II GX FPGA, $2,995 8

© 2010 Altera Corporation—Public Six Steps to Building a Video System

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. General Video System Design Flow Full Software Implementation Design Specification No Yes Project complete Software Implementation for System Bring Up OK? Hardware Implementation OK? No OK? Yes Software only change? Yes 10

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Implementation Build system incrementally in six steps  Always follow the steps! 1. Implement top-level HDL 2. Implement video output 3. Add soft processor for control and debug Can be removed later if not required 4. Implement video input 5. Implement frame sync and memory interface 6. Integrate video processing functions Full Software Implementation Design Specification No Yes Project complete Software Implementation for System Bring Up OK? Hardware Implementation OK? No OK? Yes Software only change? Yes 11

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Hardware Implementation—Video Output Test Pattern Generator Use a TPG Instead of Video Source to Test Video Output Clocked Video Output Top level (HDL) PLLs SDI-Rx VCXO PFD SDI-Tx SDI TX SDI RX DVI RX DVI Tx DVI TX SOPC Builder 12

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Hardware Implementation—Nios II Processor Test Pattern Generator Clocked Video Output Top level (HDL) PLLs SDI-Rx VCXO PFD SDI-Tx SDI TX SDI RX DVI RX DVI Tx DVI TX SOPC Builder Nios II Processor Add Nios II processor. Write Software for Control and Debug LEDs JTAG UART Buttons Add Board Peripherals 13

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Hardware Implementation—Video Input Test Pattern Generator Clocked Video Output Top level (HDL) PLLs SDI-Rx VCXO PFD SDI-Tx SDI Tx SDI Rx DVI Rx DVI Tx SOPC Builder Nios II Processor LEDs JTAG UART Buttons Clocke d Video Input Terminator Add Video Input (no datapath yet) 14

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Hardware Implementation – Memory Controller Test Pattern Generator Clocked Video Output Top level (HDL) PLLs SDI-Rx VCXO PFD SDI-Tx SDI Tx SDI Rx DVI Rx DVI Tx SOPC Builder Nios II LEDs JTAG UART Buttons Clocke d Video Input Terminator DDRX Memory Controller Frame Buffer Add Frame Buffer and Memory Controller 15

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Hardware Implementation – Video Processing Clocked Video Output Top level (HDL) PLLs SDI-Rx VCXO PFD SDI-Tx SDI Tx SDI Rx DVI Rx DVI Tx Nios II LEDs JTAG UART Buttons Clocked Video Input Add Video Processing Functions DDRX Memory Controller Chroma Resamp ler CSC Frame Buffer Deinterlacer Scaler SOPC Builder 16

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Video Design Demo Using SOPC Builder 17

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Summary Altera video design framework enables rapid development  Mix and match existing IP—leverage Altera’s open interface standard  Automatically integrate embedded processors and arbitration logic  Leverage building block IP provided by Altera  Use existing reference designs as starting points Rapid prototyping  Implement design using the appropriate development boards  Test the design with actual video signals 18

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