Project Goals (From Char. Presentation) Developing a hardware Ethernet packet generator for Ethernet network and devices testing. Support different operation modes – Stand-alone / remote controlled. Implementation of the system on Altera PCI-E Development kit board with Stratix II GX FPGA.
Project Goals (From Char. Presentation) Learning common communication protocols such as Ethernet, UDP, IP Learning HW development language and tools.
Architecture guideline: Reaching line speed Hardware Optimization: -Using fast packet memory: large on- chip MRAM for CPU. - Using fast packet memory: large on- chip MRAM for CPU. - Accelerating the packet checksum using C2H accelerator for HW implementation. - Using high speed external memory: DDR2-SDRAM and SSRAM..
Architecture guideline: Reaching line speed Hardware Optimization (cont.): -Interfacing Altera’s TSE MAC with SGDMA (instead of NIOS II directly) - Interfacing Altera’s TSE MAC with SGDMA (instead of NIOS II directly) - Increasing core clock from 83.33MHz to 150MHz..
Architecture guideline: Reaching line speed Software Optimization: -Using the UDP protocol (instead of TCP) to increase throughput performance - Using the UDP protocol (instead of TCP) to increase throughput performance - Networking with InterNiche’s “NicheStack” fully configurable networking stack and MicroC/OS-II operating system. - Raising compiler optimization level to maximum (3).
PHY Marvell External Ethernet 10/100 Mbps UDP/IP Packet generator Nios II Ethernet MAC Altera TSE MII RJ-45 Block Diagram DDR2 SDRAM/ QDR2 SRAM NicheStack UDP Networking On chip Memory Ext. CLK 100MHz PLL 100->150 MHz JTAG Debug Module SGDMA Interface JTAG
Avalon BUS NiosII Processor JTAG Debug Module JTAG UART On-chip Memory Data M Inst M SS JTAG cont. PLL SGDMA TX S Src SGDMA RX S Sink Triple speed Ethernet MAC SinkSrcS 100 Mhz 150Mhz FPGA MII SOPC Architecture On-Board Memory Controllers S
SOPC Architecture Tripple Speed Ethernet MAC Scatter-Gather DMA Controllers NIOS II CPU On-Chip Memories On-Board Memories PLL JTAG Interface CPU Timers Pipeline Bridge
Project Milestones – Part A Work Week Adjusting architecture to SIIGX with SOPC builder Learning NicheStack functions and syntax Learning MicroC OS basics Exam period winter 09’ Simulating design with basic software – transmitting UDP packets Part A final presentation and demo. 151413121110987654