1. Advanced SW/HW Optimization Techniques for Application Specific MCSoC m5151117 Yumiko Kimezawa Supervised by Prof. Ben Abderazek Graduate School of Computer Science and Engineering Adaptive Systems Laboratory September 8, 2011Research Plan Seminar1

2. Outline 1.Background 2.Problems 3.Research Goal 4.Research Approach 5.Research Schedule September 8, 2011Research Plan Seminar2

3. Background Electrocardiography (ECG) -Electrical activity of the heart -Used for diagnosis of heart disease Processing ECG signals involves heavy computation Previous proposed ECG processing system -Parallel processing using additional cores for analyzing ECG signals September 8, 2011Research Plan Seminar3

4. Background Period-Peaks Detection (PPD) Algorithm (1) Figure: A typical ECG graph September 8, 20114Research Plan Seminar

5. Period detection Peaks processing Data reading Derivation Autocorrelation Finding interval Extraction Store of results Discrimination September 8, 20115Research Plan Seminar Background Period-Peaks Detection (PPD) Algorithm (2) A. Ben Abdallah, Y. Haga, K. Kuroda, An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records, IEEE Proc. of the 39th he International Conference on Parallel Processing, San Diego, pp.99-103, Sept. 13-16, 2010.An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records

6. The system consists of mainly 2 modules Master module -Signal reading, filtering and display part PPD module -Analyzing ECG signal using Period-Peaks Detection (PPD) algorithm August 22, 20116Master's Thesis Research PlanSeptember 8, 20116Research Plan Seminar Background System Base Architecture (1)

7. 3-lead system is implemented ADC 1 ADC 12 FIR 1 FIR12 Buffer ECG Signal Analysis 1:Signal reading 2:Filtering3:Analysis4:Display 12 leads External Memory Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms Not implemented Our ideal system architecture September 8, 2011 7 Research Plan Seminar Background System Base Architecture* (2) * A. Ben Abdallah, Y. Haga, K. Kuroda, An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records, IEEE Proc. of the 39th he International Conference on Parallel Processing, San Diego, pp.99-103, Sept. 13-16, 2010.An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records Single lead3-lead Logic utilization15%38% Processing time11.209 s16.975 s

8. Problems BANSMOM runs sample data only -Can not read actual data -Difficultly in estimation of real processing time -Cannot estimate real system complexity and power Low hardware usability -The more leads, the more larger logic utilization Current driver software is not well parallelized September 8, 20118Research Plan Seminar

9. Research Goal Research about software and hardware optimization techniques for Embedded Multicore SoC (BANSMOM) -Capturing and analyzing of real ECG signals -Research about HW optimization -Parallelizing PPD algorithm (driver software) September 8, 20119Research Plan Seminar

10. Research Approach (1) Hardware/Software optimization -Hardware Adding A/D converters Fast data transfer between each memory DMA controller -Software Parallelizing Period-Peaks Detection (PPD) algorithm by refining the code and looking for parallel tasks September 8, 2011Research Plan Seminar10

11. Research Approach (2) : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory FPGA Analog ECG data from the sensor Line-in Data conversion HSMC A/D converter DMA controller September 8, 201111Research Plan Seminar

12. Evaluation Methodology Environment -Language: Verilog HDL -Tools: Quartus II, SOPC Builder, and NIOS II IDE -Target device: Stratix III DSP Board (EP3SL150F1152C2) -Sensor: Pulse wave/PCG sensor TK-701T -Target data: actual ECG signals Parameters -Hardware complexity -Processing time September 8, 201112Research Plan Seminar Stratix III Sensor

13. 201120122013 9101112123456789101112123 September 8, 201113Research Plan Seminar Investigating suitable resolution and sampling rate for A/D conversion Selecting appropriate an A/D converter Adding the A/D converter into the system Getting actual data using the sensor Adding DMA controller into the system Optimization of software Verification of the system Writing master’s thesis Research Schedule

14. Thank you for listening September 8, 201114Research Plan Seminar

15. September 8, 2011Research Plan Seminar15

16. 16 Period detection Peaks detection Reading data Derivation Autocorrelation Find interval Extraction of max point Store results Discrimination Research Plan Seminar Based on autocorrelation approach Research Approach (2) Parallelizing this phase September 8, 2011

17. 201120122013 9101112123456789101112123 September 8, 201117Research Plan Seminar Investigating suitable resolution and sampling rate for A/D conversion Selecting appropriate an A/D converter Adding the A/D converter into the system Getting actual data using the sensor Adding DMA controller into the system Optimization of software Verification of the system Writing master’s thesis Research Schedule