1. Ethernet Bomber Ethernet Packet Generator for network analysis Oren Novitzky & Rony Setter Advisor: Mony Orbach Started: Spring 2008 Part A final Presentation

2. Project Goals Developing a hardware Ethernet packet generator for Ethernet network and devices benchmarking. Support stand-alone operation modes with several user configurations. Implementation of the system on Altera PCI-E Development kit board with Stratix II GX FPGA.

3. Project Goals Learning common communication protocols such as Ethernet, UDP, IP Learning HW development language and tools. Building SW application to support HW design.

4. Architecture guideline: Hardware Optimization: - Accelerating the NIOS by implement large instruction/ data cache. - Using high speed external memory – DDR2 -Interfacing Altera’s TSE MAC with SGDMA (instead of NIOS II directly) - Interfacing Altera’s TSE MAC with SGDMA (instead of NIOS II directly) - Increasing core clock from 83.33MHz to 100MHz using only one PLL.

5. Architecture guideline: Software Optimization: -Using the UDP protocol (instead of TCP) to increase throughput performance - Using the UDP protocol (instead of TCP) to increase throughput performance - Networking with InterNiche’s “NicheStack” fully configurable networking stack and MicroC/OS-II operating system. - Raising compiler optimization level to maximum (3).

6. PHY Marvell External Ethernet 10/100 Mbps UDP/IP Packet generator Nios II Ethernet MAC Altera TSE MII RJ-45 Block Diagram DDR2 SDRAM NicheStack UDP Networking On chip Memory Ext. CLK 100MHz DDR2 HP Controller + PLL @ 200MHz JTAG Debug Module SGDMA Interface JTAG Flash memory Flash HP Controller NIOS II terminal

7. SOPC Architecture FPGA NiosII Processor Data M JTAG Debug Module Inst M Pipeline bridge S M I/O – timer, LED, buttons S DDR2 HP Controller + PLL @ 200 MHz S HR @100Mhz FR @200Mhz Flash controller S SGDMA TX S Src SGDMA RX S Sink Triple speed Ethernet MAC SinkSrc S On-Board Memory Controllers S

8. SOPC Architecture

9. Conclusions A single PLL should be used for all components in the system (not necessarily at the same freq). A single PLL should be used for all components in the system (not necessarily at the same freq). For Ethernet applications it’s necessarily to use the flash memory – MAC address. For Ethernet applications it’s necessarily to use the flash memory – MAC address. When using several components working at different speeds it’s recommended to use a pipeline bridge in order to sync them all. When using several components working at different speeds it’s recommended to use a pipeline bridge in order to sync them all. Using external SDRAM memory in order to free on chip memory for caching. Using external SDRAM memory in order to free on chip memory for caching.

10. Part B goals – software development Building NIOS II UDP packet generator application: Building NIOS II UDP packet generator application:  Support user defined payload - data and size.  Support user defined packets - number and timing. Building remote station UDP packet receiver for analyzing performance. Building remote station UDP packet receiver for analyzing performance.

11. Project Milestones – Part B Work Week Final part A presentation Application development Application testing and debug 48474645444342