2. Interface of DSP to Peripherals of PC Spring 2002 Supervisor: Broodney, Hen | Presenting: Yair Tshop Michael Behar בס " ד

3. General Description בס " ד Project goal: Connecting The TI DSP to the computer Peripherals in order to connect the Peripherals to a computer through a Blue Tooth. Peripherals : Parallel port can use printers Rs232 com port 2 Ps/2 for mouse and KeyBoard

4. Implementation Architecture בס " ד

5. Architecture Considerations The board has two functions :serving as host and serving as target.Special care has been given to unite common resources. As there are several units that communicates with the McBSP, an internal bus strategy has been chosen. בס " ד

6. Architecture considerations cont. The design permits adding and removing peripherals blocks easily by maintaining a modular structure. The board was designed to enable loop backs בס " ד

7. Parallel block בס " ד

8. Parallel block implementation Two units :HCA & TCA The FIFO resource is common to the HCA and TCA. Each unit contains an E ncoder & D ecoder. Changes in the control and data lines are coded into events. בס " ד

9. The Controller The controller is responsible for managing the arbitration of the internal bus. Each peripherals gets a part according to its bandwidth’s weight. A round robin insures that there will be no starvation. בס " ד

10. The McBSP block בס " ד

11. McBSP block tasks Full Duplex  Rx and Tx Models Multi channel operation (TDM) Each peripheral gets channels according to its bandwidth. Tx Model: Transfer Byte as serial bits Fit each Byte in its appropriate slot. Rx Model: Receive The bits and ensemble a Byte Produces a target address. בס " ד

12. RS232 block בס " ד

13. RS232 cont. This block is based on a UART Core - a_6402 Surround interface to suit the core with the design The block demands coping with two clock domains. בס " ד

14. PS2 2 ps2 ports enables the use of mouse and keyboard. 2 controllers : Host controller Target controller. Host is master but Target is generating the clock בס " ד

15. Ps2 cont. One data line for Host and Device so the controllers must never cause a clash. Controllers must buffer data while other side is transmitting. בס " ד

16. System The board has a FPGA (ALTERA) and a configuration device (EPC2). The TI DSK is connected to the Target and Host Board through 2 McBSP ports 1 full loop back board and 1 host side board

17. Final result 2 Boards. One Loop back board and one host board. Software for TI processor Ps2 – two port active RS232 – one port active Paralle – one port active McBSP – two port full duplex active

18. Verification Each block in the design was simulated separately to insure logic correctness. Full system simulation. Device and host models were built to create a test environment. בס " ד

19. From design to the real world Electrical tests of the boards Divide and conquer strategy: One board loop-back Each protocol by itself Adding TI to the game Adding the second board בס " ד

20. Validation Using the Logic analyzer to monitor the flow of information between the devices Using the logic analyzer as an online checker By defining the trigger to catch illegal states. בס " ד

21. Debug Examples Glitches on parallel lines coming from the printer were fixed by internal logic filters Noise on McBSP lines from the DSP: Hardware solutions Logical solution Optimization on TI C code. בס " ד

22. Conclusions There is a difference between logic simulation and the real system. The debugging foundation is important The main task in debugging is to find the problem. Divide and conquer strategy has proved itself. The guidance lectures helped us. בס " ד

23. We would like to thank Hen Broodney The Lab’s staff AND our families בס " ד