1. © 2008 Altera Corporation—Public How to Facilitate Advanced Digital Signal Processing (DSP) Design When Facing Performance and Time-to- Market Challenges

2. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2 Agenda FPGA-based digital signal processing (DSP) trend New Altera ® FPGA devices for DSP application Intellectual property (IP) cores that facilitate DSP design FPGA-based DSP design flow A typical application example—repeater application Resources available Conclusion

3. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3 DSP is a strategic area of investment for Altera  Large available market  FPGAs have excellent DSP performance per $  The market demands high performance Altera and DSP “Digital signal processing (DSP) has become the technology driver for the entire semiconductor industry. The high-performance segment of the DSP market is growing the fastest, led by FPGAs.” --Will Strauss, Forward Concepts 0 200 400 600 800 1,000 1,200 1,400 1,600 200520062007200820092010 DSP in FPGA ($M)

4. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4 Altera and DSP Depth of DSP offering and system complexity 20022004200620082010 DSP FPGA devices DSP intellectual property DSP tool flows Application- specific reference designs FPGAs become optimized for DSP Today: General-purpose DSP Video and image processing Wireless functions Floating-point library Tomorrow: More efficient IP cores, use in multiple tools Today: Wireless: RF DDC/DUC Video monitoring Tomorrow: SDR systems and methodology Compression Today: Model-based design Embedded systems design C-based design Tomorrow: Higher levels of abstraction and QoR Today: Cyclone ® III FPGAs Stratix ® III FPGAs Tomorrow: Planning for even more DSP performance into 45 nm and 32 nm Altera providing complete DSP solutions

5. © 2008 Altera Corporation—Public New Altera FPGA Devices for DSP Application

6. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 6 Announcing Altera’s New 40-nm Devices 6

7. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7 DSP Block Multiplier Capabilities LEs18x18 multipliers Extended precision (18x36) multipliers SP floating point (36x36) multipliers Stratix IV GX FPGA EP4SGX7072,60038419296 EP4SGX110105,600512256128 EP4SGX230232,7501,288644322 EP4SGX310306,800832416208 EP4SGX380374,4001,040520260 EP4SGX570569,6001,024512256 Stratix IV E FPGA EP4SE110105,600512256128 EP4SE230232,7501,288644322 EP4SE310306,800832416208 EP4SE380374,4001,040520260 EP4SE570569,6001,024512256 EP4SE720717,6001,360680340

8. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8 Performance Through Parallelism 72 Total 18X18 multipliers = 1,360 EP4SE720 Maximum clock frequency = 550 MHz DSP performance = 1,360 * 550 MHz 748 GMACS

9. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9 + Optional pipelining Output register unit Output multiplexer +-  +-  Input register unit 144 72 -Confidential +- +- +- Optional pipelining +-  144 R + Output multiplexer Optional RND and SAT unit Output register unit Input register unit R +- +- +- Optional pipelining +-  144 R + Output multiplexer Optional RND and SAT unit Output register unit Input register unit R 72 Stratix II FPGA Stratix IV and Stratix III FPGAs Cascade modes  Input cascade  Output cascade Rounding  Unbiased and biased Saturation  Asymmetrical and symmetrical Barrel shifter  Arithmetic, logical, and rotation Basic multiplier modes  8 x (9x9)  6 x (12x12)  4 x (18x18)  4 x (18x36)  2 x (36x36)  2 x complex (18x18) Multiply and sum modes  4 x sum of two (18x18)  2 x sum of four (18x18) Accumulation  2 x Acc Basic Multiplier Modes  8 x (9x9)  4 x (18x18)  1 x (36x36)  1 x complex (18x18) Accumulation  2 x Acc Rounding  16-/32-bit biased Saturation  32-bit asymmetrical Barrel shifter  Partial support The Stratix DSP Block Evolution

10. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10 Highest Performance DSP Capabilities Up to 1,360 18x18 embedded multipliers with Stratix IV GX FPGA

11. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11 Highest Performance DSP Capabilities Memory ports (18-/36-bit) in DSP-enhanced families Stratix III E FPGA Stratix IV E FPGA 0 400 800 1,200 1,600 2,000 2,400 2,800 3,200 0100,000200,000300,000400,000500,000600,000700,000800,000 40% MORE MEMORY BANDWIDTH Over 3,000 embedded memory ports (18-bit/36-bit) with Stratix IV GX FPGA

12. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12 Highest Performance DSP Capabilities Registers/multipliers in DSP-enhanced families Stratix III E FPGA Stratix IV E FPGA 0 50 100 150 200 250 300 350 400 450 500 0100,000200,000300,000400,000500,000600,000700,000800,000 Up to 445 registers Per multiplier Significant register resources for DSP applications

13. © 2008 Altera Corporation—Public IP Cores That Facilitate DSP Design

14. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 14 General DSP IPs FIR compiler CIC compiler FFT/IFFT compiler Error correction Reed-Solomon Encoder/decoder compiler Signal generation NCO compiler Viterbi Parallel/serial decoder Altera DSP IP Portfolio Video Imaging Processing Suite Gamma correction Line buffer compiler 2D FIR filter BT656  Avalon ® ST Video 2D median filter Color space converter Chroma resamplerAvalon ST Video Alpha blending mixer ScalerDeinterlacer Color plane sequencer Frame buffer image clipper FilterTransform Error correction Signal generation New

15. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 15 General DSP Design Examples For more information on design examples, visit: www.altera.com Wireless  Polyphase modulation with aliasing for digital up-conversion  Cyclic prefix insertion for orthogonal frequency division multiplexing ( OFDM) systems  Designing digital down conversion systems using CIC and FIR filters  Using CIC decimation filter with multi-channel support Filters  CIC interpolation filter with multi-channel data support Transforms  Achieving unity gain in FFT/IFFT pair using block floating-point arithmetic scaling Forward error correction (FEC)  Bit-error rate (BER) performance measurement of Viterbi decoder  Viterbi decoder with node synchronization

16. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 16 FIR CIC FIR Signal Processing Chain in FPGAs Digital Up and Down Conversion: Wireless, Medical, Test and Measurement, Military Altera’s DSP cores let you quickly build a complete up/down conversion signal chain  Numerically controlled oscillator (NCO), cascaded integrator comb (CIC), finite impulse response (FIR) filters using the Avalon streaming interface  Optimized Altera DSP blocks (multiplier and accumulator) NCO ∑ FIR CIC FIR NCO To DAC From ADC I Q I Q Digital up converterDigital down converter Altera DSP IPAltera DSP blocks

17. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 17 IP for Wireless Applications Altera’s DSP IP functions allow seamless integration with proprietary wireless chain building blocks  Reed-Solomon and Viterbi FEC Multiple reference designs and design examples are available to give you a jump start and explore your design options  Designing digital down conversion systems using CIC and FIR filters  Digital predistortion reference design  Channel estimation and equalization reference design Altera DSP IPAltera DSP blocks FIR CIC FIR NCO ∑ FFT adc Channel estimation and symbol demapping Deinter leaver FEC decode – Viterbi or Turbo

18. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 18 Using Altera VIP Cores: Quartus II Software VIP cores are configurable using Quartus ® design software

19. © 2008 Altera Corporation—Public FPGA-based DSP Design Flow

20. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 20 System-level simulation of algorithm model MATLAB/Simulink RTL implementation RTL simulation Precision, Synplify, Quartus II software, ModelSim ® tool System-Level Design DevelopmentImplementation System-level verification of hardware implementation Altera FPGA Altera development kits Verification System, algorithm, and FPGA design separated Algorithm modeling (C/C++,M,MDL) Synthesis place-and-route simulation (VHDL/Verilog) System-level verification (Programming file)

21. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 21 Interactive environment and high-level language In MATLAB you can:  Develop algorithms and applications  Analyze and access data  Visualize data  Perform numeric calculations  Document and publish results MATLAB

22. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 22 Dynamic graphical modeling environment add-on to MATLAB In Simulink you can:  Dynamically develop entire systems  Simulate and interact with the system  Explore architectures  Analyze results  Generate device-specific code Simulink

23. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 23 Toolboxes What is DSP Builder? MATLAB and Simulink  An environment for algorithm development and analysis Provides static and bit-true models Develop and test individual components  A graphical environment for system modelling Provides dynamic and bit/cycle-true models Tests component interactions and behavior of whole systems DSP Builder: library add-on for Simulink  Common DSP functions and advanced IP for FPGA  Register transfer level (RTL) generation and FPGA compilation utilities  FPGA debug facilities Altera DSP-optimized FPGAs  Stratix III devices  Cyclone III devices Floating Point Simulation Signal Compiler MDL Schematic GenericSimulink Blocks Fixed Point Conversion with AlteraBlockset Fixed Point Simulation SimulinkDesign Entry DSP Builder Floating-point simulation Signal compiler MDL schematic genericSimulink blocks Fixed-point conversion with Alterablockset Fixed-point simulation Simulinkdesign entry DSP Builder

24. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 24 DSP Builder Design Flow MATLAB/Simulink domain (System simulation and verification) HDL/hardware domain ( Hardware implementation/RTL simulation)

25. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 25 Design Flow Steps 1. Create a Simulink model using Altera’s library blocks 2. Simulate the design and verify the functionality 3. (Optional) Perform RTL simulation for comparison with the original model 4. Use the signal compiler to compile the FPGA 5. Program a development kit or board 6. Debug the hardware using SignalTap ® II logic analyzer or hardware in the loop

26. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 26 Step 1: Create a Simulink FPGA Model Drag and drop Altera’s library blocks into Simulink Parameterize each block or IP function

27. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 27 Parameterize DSP MegaCore IP DSP IP is parameterized through the normal MegaCore ® IP flow

28. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 28 Step 2: Simulate in Simulink Using all the facilities of MATLAB and Simulink:  Create design stimulus  Run the Simulink simulator  Instrument your design MATLAB and Simulink stimulus MATLAB and Simulink instruments

29. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 29 Step 3: (Optional) Verify the Generated RTL Automatically generate RTL, run in ModelSim, and compare to Simulink

30. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 30 Step 4: Compile the FPGA *.mdl Synthesis Placement and routing Automatically synthesize, perform placement and routing, and generate an FPGA programming file *.pof

31. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 31 Step 5: Program a Device on a Board Automatically program a device on a development kit or board *.pof

32. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 32 Step 6: Debug with SignalTap II Logic Analyzer Embed a logic analyzer, capture live data, and analyze results in MATLAB/Simulink JTAG

33. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 33 Step 6: Debug/Simulate with HIL Use a FPGA for simulation acceleration or logical verification Your design JTAG

34. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 34 Design Flow Steps—Review 1. Create a Simulink model using Altera’s library blocks 2. Simulate the design and verify the functionality 3. (Optional) Perform RTL simulation for comparison with the original model 4. Use the signal compiler to compile the FPGA 5. Program a development kit or board 6. Debug the hardware using SignalTap II logic analyzer or hardware in the loop

35. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 35 DSP Builder Advanced Blockset Advantages Automatic pipelining to meet required f max Similar performance as optimized HDL Easy timing closure Fewer compile iterations Effortless FPGA implementation Fast design space exploration Fast multi-channel design implementation Automatic generation of control plane logic Efficient pipelining for multi-channel datapaths Ability to update design by editing system-level parameters Effortless FPGA device family retargeting

36. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 36 Understanding DSPB-AB With a Design Built With Primitive Start with a textbook representation of a design Build a Simulink design using identical building blocks from DSP Builder Simulate the design using Simulink Add the number of channels, simulate Target the right FPGA family and compile … let’s see this with an example

37. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 37 Start with a textbook representation …

38. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 38 Map the Textbook Representation to Simulink

39. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 39 Build the Top-Level Simulink Design

40. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 40 Choose the Top-Level Parameter… Simulate

41. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 41 Choose the Target Device Family and Compile

42. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 42 Design Done in Hardware: >400-MHz Performance

43. © 2008 Altera Corporation—Public A Typical Application Example— Repeater Application

44. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 44 Wireless Cellular Repeater Definition Repeater [from Wikipedia]: A repeater is an electronic device that receives a weak or low-level signal and retransmits it at a higher level or higher power, so that the signal can cover longer distances without degradation Wireless cellular repeaters: A kind of repeater that receives weak or low-level radio frequency signals from cellular networks and retransmits the signals at higher level or higher power. Wireless cellular repeaters are typically used to boost cell phone reception to areas where signal coverage by the infrastructure cellular network is weak

45. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 45 Basestation signal source Extended coverage Repeater donor unit Repeater remote unit Fiber-Optic Repeater

46. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 46 PA DonorRemote FPGA implementation Optical Repeater Diagram DuplexerCPRI DDC DUC ADC DAC SERDES E/O O/E CPRI SERDES DUC DDC DAC ADC Duplexer

47. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 47 Reference Design Overview DUC/DDC  Provides the link between digital baseband and analog RF front end of generic transceiver  High-throughput signal processing required makes FPGA ideal platform RF Front-end Baseband processing ADC DDC DAC DUC RF IF Baseband

48. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 48 GSM Digital IF Solution

49. © 2008 Altera Corporation—Public Resources Available

50. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 50 DSP Design Examples More at http://www.altera.com/support/examples/dsp/exm-dsp.html FunctionDesign Entry Method Achieving Unity Gain in Block Floating Point IFFT+FFT Pair Coefficient Reload FIR Filter Polyphase Modulation With Aliasing for Digital Up-Conversion Implementing OFDM Modulation and Demodulation Designing Digital Down Conversion Systems Using CIC and FIR Filters Using CIC Decimation Filter With Multi-channel Support CIC Interpolation Filter With Multi-Channel Data Support Deinterlacer Using Weave Mode Deinterlacer Using Bob Mode Gamma Correction YCbCr to RGB Color Space Conversion Image Frame Resizing Using Scaler Salt and Pepper Noise Removal Using 2D Median Filter Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer Chroma Resampler Up-Conversion 2D Sharpening Finite Impulse Response (FIR) Filter Altera hardware description language (AHDL) VHDL MAX+PLUS ® II graphic editor Verilog hardware description language (HDL) Tool command language (Tcl) Quartus II development tool Simulink model

51. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 51 Cyclone III Video Kit http://www.bitec.ltd.uk/ciii_video_dev_kit.html Altera EP3C120F780 development board Bitec HSMC quad video daughtercard  8 composite or 4 s-video inputs  1 high-definition (HD) (1080p) digital video interface (DVI) output port or  1 TV (PAL/NTSC) output with resolutions to 1024x768 and support for composite, s-video, or SCART (RGB) outputs Bitec HSMC DVI daughtercard  1 HD (1080p) DVI output port (HDMI with external adaptor)  1 HD (1080p) DVI input port (HDMI with external adaptor) Interfaces directly to the Altera Video and Image Processing (VIP) Suite

52. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 52 http://www.altera.com/products/devkits/ altera/kit-dsp-professional.html Stratix II GX Video Kit Stratix II GX video development board with an EP2SGX90 Video interfaces  DVI inputs/outputs  Four (4) standard definition (SD)/HD SDI inputs/outputs, including dual- link SDI support  Asynchronous Serial Interface (ASI) inputs/outputs Audio interfaces  AES3  Sony/Phillips digital interface (S/PDIF) External memory  DDR2 DIMM (72 bit at 266 MHz)  2-Mbyte SRAM  16-Mbyte flash (configuration) Available now $4,995

53. © 2008 Altera Corporation—Public Conclusion

54. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 54 Conclusion DSP-based FPGA market will become $1.6B in 2010 Altera is first with 40-nm FPGAs: Stratix IV FPGAs deliver highest DSP performance at the lowest power General IP cores and VIP Suite facilitate customers’ designs Simulink+DSP Builder bridges the gap between algorithm and hardware development, enhances productivity for FPGA hardware design, and makes FPGAs accessible for non-FPGA-experienced engineers

55. © 2008 Altera Corporation—Public Backup

56. © 2008 Altera Corporation—Public Altera Video Design Example 1

57. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 57 Lay Down the Different Functions of the Video Signal Chain Build the first version of your video signal chain using the Altera video IP building blocks SDI in Function 2 Function 3 SDI out Function 1 Function 4

58. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 58 Connect the Blocks Using the Avalon ST Interface Protocol SDI in Function 2 Function 3 SDI out Function 1 Function 4 Avalon ST video interface

59. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 59 Add the Memory Subsystem and Frame Buffer Controller SDI in SDI out Function 1 Function 4 Avalon Memory Mapped interface and arbitration DDR memory controller Function 2 Function 3

60. © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 60 Add an On-Chip Micro-Controller SDI in SDI out Function 4 Function 2 Function 3 DDR memory controller Function 1