1. Towards the Design of Heterogeneous Real-Time Multicore System m5151117 Yumiko Kimezawa February 1, 20131MT2012

2. Background (1/5) Electrocardiography (ECG) is a well known method for heart diagnosis -Used as one of major diagnosis for conventional health monitoring Main challenges of processing ECG arise from: -High computational demand for processing huge amount of data under:  Strict time constraints  Relatively high sampling frequency  Life critical conditions February 1, 2013MT20122

3. February 1, 2013MT20123 Most ECG systems use Pan-Tompkins approach based on QRS complex o Usage of R-peak as a reference point o Accurate detection of R-peak is a must  R-peak detection might be inaccurate Traditional techniques may fail in detecting serious heart problems Background (2/5)

4. February 1, 2013MT20124 Most ECG systems use Pan-Tompkins approach based on QRS complex o Usage of R-peak as a reference point o Accurate detection of R-peak is a must  R-peak detection might be inaccurate Traditional techniques may fail in detecting serious heart problems Background (2/5)

5. February 1, 2013MT20125 Most ECG systems use Pan-Tompkins approach based on QRS complex o Usage of R-peak as a reference point o Accurate detection of R-peak is a must  R-peak detection might be inaccurate Traditional techniques may fail in detecting serious heart problems Background (2/5)

6. Background(3/5): BANSMOM System February 1, 2013MT20126 System Architecture of BANSMOM System Stratix III Real-time monitoring interface Verification R y : Autocorrelation function y[n]: The filtered ECG signal L: Lags of the calculations to get the period PPD algorithm -Autocorrelation

7. Background (4/5) February 1, 2013MT20127 Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory ECG Data Rom : Data flow : Control signal : Data flow : Control signal Master module -Controlling the whole systems such as reading date from shared memory, etc PPD module -Detection of following information using PPD algorithm  Intervals and their position  Position and voltage of each peak (P, Q, R, S, T and U) Figure: Block diagram of 3-lead system

8. 8 Period detection Peaks detection Reading data Derivation Autocorrelation Find interval Extraction of max point Store results Discrimination Based on autocorrelation approach Background (5/5) : PPD Algorithm February 1, 2013MT2012

9. Problems Requiring a large amount of hardware resources -Logic utilization shows a linear increase for each additional PPD modules PPD Algorithm runs on single processor  may miss Real-Time deadlines The need for connecting to database server in order to monitor data efficiently in real-time February 1, 2013MT20129

10. Research Goals 1.Software Optimization  Parallelize PPD algorithm to boost performance and meet real-time deadlines 2.Hardware Optimization  Optimize system hardware (Sharing, DMA and Ethernet cores) 3.System Integration ▪Integrate and evaluate the new optimized system with a Real-Time Monitoring Interface (being Developed by Achraf) February 1, 2013MT201210

11. Graphic LCD Controller Master CPU Memory Master CPU Timer Graphic LCD LED JTAG UART PPD Module Master Module LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU Filtered Data Memory Shared Memory ECG Data Rom : Data flow : Control signal DMA Controller Ethernet Module Ethernet PHY TSE MAC TX SGDMA Descriptor Memory The Block Diagram of improved system February 1, 201311MT2012

12. The Broad layout of N-lead System February 1, 2013MT201212 PPD module 1-lead 2-lead 3-lead N-lead Ethernet PHY Master module, Ethernet module Graphic LCD Input Output

13. Evaluation methodology Language: Verilog HDL Tools: Quartus II, SOPC Builder, and NIOS II IDE Target device: Stratix III DSP Board (EP3SL150F1152C2) Target data: 10 sample data -From MIT-BIH Normal Sinus Rhythm Database Evaluation approach -Hardware complexity -Execution time February 1, 201313MT2012

14. Hardware Complexity February 1, 2013MT201214 System model Logic utilization Block memory bits Fmax (MHz) Power (mW) Combinational ALUTs Memory ALUTs Dedicated Logic registers Total 1-lead12,38819415,33618%1,368,920(24%)90.99696.35 2-lead20,24621825,23131%1,971,992(35%)94.33730.23 3-lead28,27023835,15343%2,575,064(46%)88.39766.37 4-lead36,24025845,02455%3,178,584(56%)94.10792.70 5-lead44,161054,27867%3,783,066(67%)86.01814.52 6-lead52,060064,06679%4,386,330(78%)86.07826.88 7-lead66,496082,356104%4,972,866(88%)N/A

15. Execution Time February 1, 2013MT201215 The following table shows the average execution time 10 kinds of sample data is used to calculate that time Comparing the execution time of improved system including the feature of DMA transfer to execution time of previous system Architecture Improved SystemPrevious System 1-lead 2-lead 3-lead 4-lead

16. Conclusion Optimizing hardware part by adding DMA feature to previous system Optimizing software to boost performance and meet real-time deadlines (not yet) Processing time is decreased by (not yet) -XXX % in improved system February 1, 2013MT201216

17. Future Work Integrating and evaluating the new improved system with a Real-Time Monitoring Interface February 1, 2013MT201217

18. Thank you for listening February 1, 2013MT201218

19. 19 Period detection Peaks detection Reading data Derivation Autocorrelation Find interval Extraction of max point Store results Discrimination Based on autocorrelation approach Background (3/5) : PPD Algorithm February 1, 2013MT2012

20. Research Schedule February 1, 2013MT201220 TaskDateStatus Investigating DMA transfer ○ Investigating how to transfer data using Ethernet ○ Minor modification of software November, 2012 ○ Adding DMA controller ~ December, 2012 × Adding Ethernet module ~December, 2012 × Modification of software ~ January, 2012 × Performance evaluation ~ January, 2012 × Writing thesis ~ January, 2013 ×