Camera Auto Focus Presentation 4, February 14 th, 2007 Team W1: Tom Goff (W11) David Hwang (W12) Kate Killfoile (W13) Greg Look (W14) Design Manager: Bowei Gai Project Goal: Design a low-power, small auto focus chip for a camera or other hand-held device

Status Last Time –Verilog implementation –Revised floor plan –Major architecture revision This Week Exhaustive simulations Schematic Power testing In Process… Power control logic implementation Schematic simulations Unfinished Layout Extraction, LVS, post-layout simulation

Sense Amp Flip Flops Initial power simulations indicate sense amps are a good choice Plus, it bolsters weak input signals

Other Design Decisions Lots of logic optimizations Distribute power logic

Transistor Count ComponentFull Chip Count Registers1,600 Comparators2,100 FP multiplier3,000 FP adder2,000 Subtractors2,000 Int to float logic1,040 Power control2,000 Buffers2,000 Muxes2,480 Total~18,220 Still fluctuating…

Updated Floor Plan

Testing of Components Remember our C Implementation? We used this to exhaustively test our Verilog.

Exhaustive testing ComponentInputsSimulation Time FP Multiplier3*2^203 minutes FP Adder2^202 minutes Complete circuit 2^17< 1 minute

Detailed results

Schematic Finished all smaller modules Left to wire: –FP Multiply –Global module

Next Steps Finish schematic simulations Continue optimizing logic Implement power logic control

Problems Full adder simulations 493 MB text files crash your shell Fierce competition for white board space; many deaths Communicate naming conventions

Questions

References Sense Amp FF’s: The green book from