1. Camera Auto Focus Presentation 7, March 7 th, 2007 Team W1: Tom Goff (W11) David Hwang (W12) Kate Killfoile (W13) Greg Look (W14) Design Manager: Bowei Gai Project Goal: Design a low-power, small auto focus chip for a camera or other hand-held device

2. Status Last Time –Schematic testing –Control logic structural Verilog This Week Rigorous schematic testing Control logic structural Verilog Sub-module layout In Process… Layout Extraction, LVS Control logic Unfinished Post-layout simulation

3. Design Decisions Concentrated on layout decisions

4. Same Transistor Count ComponentFull Chip Count AG Preprocessor2,274 Delta I Preprocessor2,624 FP multiplier5,832 FP adder994 Power control~1,000 Buffers2,000 Total~17,182

5. Modified SERF Adder Power Analysis: Normal 5 gate FA: ~16 uW T gate FA: 9.127 uW SERF: 6.834 uW

6. Adder Layout

7. Wang’s XOR and XNOR

8. Int to Float

9. Integer Compare

10. Floating Point Compare

11. Sample Shifter

12. AG Preprocessor

13. Floating Point Adder

14. Muxes

15. Integer Multiplier…so far

16. Next Steps Spring Break! Continue laying out, extracting and LVS’ing modules Complete control logic

17. Problems Beginning to realize how useful floorplanning is; difficult to follow it Other professors; selfishly want us to work on their class Curiosity about “glass” layer caused 2450 DRC errors *cough* Greg *cough*

18. Problems II XORs and XNORs named Wang; endless amusement for mature group members

19. Questions

20. References None this week