1. A Digital Circuit Toolbox

2. Verilog Hierarchy
Each design identifier creates a new branch of the hierarchy tree

3. Tristate Signals and Busses
Tristate busses are allowed by most FPGA architectures on devices output pins
If tristate are not allowed, the synthesis may have control to automatically substitutes with MUXes

4. Schematics for Internal Tristate Buffer Design

5. MUX version of Tristate Buffer Design

6. Bidirectional Busses The signals is divided into two parts:
the driver part
input part
The two parts are then wired together

7. Bidirectional Busses

8. If/else Priority Encoder
Implied priority with precedence assigned to the first instruction encountered in a begin/end block

9. If/else Priority Encoder

10. Case Priority Encoder
The cases are mutually exclusive and do not overlap

12. State Machines Use a set of registers,
to determine current machine state
Moore style : the output depends only on the state
Mealy style: the output depends on the state and some input signals

13. State Machines

14. State Machines

15. Converting Binary to Gray Code

16. Converting Gray Code to Binary

17. State Assignment
Make a big difference in how efficiently your logic will be synthesize
use parameters, ‘define and ‘ifdef to select between encoding assignments

18. State Assignment
One-hot state assignment means that each state is assigned a single state flip-flop which is active only in the assigned state
One-could state assignment means that a flip-flop is inactive only in the assigned state

19. Adders Half-Adder
The synthesis tool will examine each instance of the operator and will try to implement the logic with a preoptimized module

20. Half-Adder

21. Full Adder
To turn the half adder into a full adder, we take the output of a half adder and connect it into another half adder

22. Full Adder

23. Full Adder

24. Full Adder

25. Subtractor
Similar to the adder

26. Full-Subtractor

27. Hard-Wired Multipliers
Multiply value by a constant
The multiplication process shifts and adds

28. Generic Multipliers
We must create logic which allows all the shift and adds to be used