[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Nov. 19 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

Old Version

Current Version

Schematic Simulation

After discussion, we found the global routing is still hard due to some issues.( spacing between wires, order of inputs.) Fix the layout version, to make the global routing more easier. Wider than before, and fix a little floorplan also.

Real time counter, lots user defined inputs and comparator.

Combine them together. Output to Tom’s FSM

Global Routing  Working on global routing for 2:1 MUX to two 16:1 MUX.  Floor plan is changed a little bit for fitting wires.

Global Routing Tons of wires over here. Less than one third wires are connected. Leave some space for safety.

Issue  It’s really painful. Still don’t know how long will it take.  Would that be fine by using metal 1 for part of global routing to save area?