1. Noise Canceling in 1-D Data: Presentation #4 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Feb 14 th, 2005 Gate Level Design Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan: –Structural Verilog (Done) –Revised Floorplan (Done) To be done: –Schematics (85%) –Layout (5%) –Spice simulation

3. Previous Block Diagram

4. Final Block Diagram

5. Structural Verilog Output Behavioral Verilog Output Structural Verilog Output Similar Output Values. Differences due to 16-bit Floating Point Units

6. Result Comparison

7. New Transistor Count… Part Last Week’s Transistors New Transistors 16-bit FPA5x1700 = 85003x 4154 = 12462 16-bit FPM3x2028 = 60843x 3858 = 11574 Registers10x16x14 = 22407x16x14 = 1568 ROM800 Converter2x312 = 624 MUX/DEMUX384 Adder248 Counter214 Alternator64 Total ≈ 19146 + Misc ≈ 22000 ≈ 27938 + Misc ≈ 30000

8. Area Estimates PartLast week’s Area (µ²)New Area (µ²) 16-bit FPA5x140x110 = 770003x140x140 = 58800 16-bit FPM3x140x106 = 445203x170x170 = 85800 16-bit Register10x33x24 = 79207x33x24 = 5544 ROM43x180 = 7740 MUX/DEMUX6x6.8x57 = 2325.6 Converter2x20x40 = 1600 Counter1004.5 Adder28x35 = 980 Alternator1x48 = 48 Total ≈ 143138 µ² + Misc ≈ 190000 µ² ≈ 163842µ² + Misc ≈ 200000 µ²

9. Revised Floorplan

10. Mux 16-bit 2:1 Layout

11. Schematics

12. ROM

13. Alignment Shifter

14. Leading Zero Counter

15. Rounding Unit

16. Normalizing Unit

17. Wallace Tree Multiplier

18. Input of ROM Table Testbench

19. Test Results for Sine Time = 40ns Input: 2.52 (21 st value) SinOutput: 00110001 = 0.5823

20. Test Results for Cosine Time = 40ns Input: 010100 (21 st value) CosOutput: 10110101 = -0.8130

21. Critical Path Estimation Cycle 2 will be longer than Cycle 1 because it uses 3 FPM + 2 FPA while Cycle 1 uses 2 FPM + 3 FPA

22. Last week’s challenges… Finalizing out designs for the floating point adders and multipliers –Wallace tree multiplier vs Array multiplier Choose Wallace implementation because it saves 10% of power –Leading zero counter for normalizing block Found a smaller implementation of the normalizing block

23. This week’s challenges… Completing and Testing Top level Schematic Creating Layouts for Floating Point Multipliers and Adders with different shapes Clock Skew and other Timing issues Transistor count .. again..

24. Questions?