Liaison Report September 2011 North America 3DS-IC Committee (Three-dimensional Stacked Integrated Circuits) Liaison Report September 2011 NA 3DS-IC Committee Report - September 2011

Outline 3DS-IC Committee Background 3DS-IC Leadership & Organization Overview of Task Forces Current Activities Upcoming Meeting Schedule NA 3DS-IC Committee Report - September 2011

3DS-IC Standards Committee Charter To explore, evaluate, discuss, and create consensus-based specifications, guidelines, and practices that, through voluntary compliance, will; promote mutual understanding and improved communication between users and suppliers of 3DS-IC materials, carriers, automation systems and devices, and enhance the manufacturing efficiency and capability and shorten time-to-market so as to reduce manufacturing cost in the 3DS-IC industry. Committee formed in Fall 2010 Inaugural meeting held in January 12, 2011 NA 3DS-IC Committee Report - September 2011

Participating Companies* Over 140 registered TC members 3MTS AllVia Altera AMD Amkor Applied Materials ASE Attoscopy Brewer Science BroadPak Brooks Automation CEA/LETI Corning DISCO Dynaloy Entegris Epistar eSilicon EVG Fraunhofer GLOBALFOUNDRIES IBM IMEC Intel ITRI KLA-Tencor KYEC Lintec Maxim Micron Miraial Monolithic (NuPGA) Neocera Nikon NIST Novellus Olympus-ITA PEER Group Planarity Qualcomm Raytex Rudolph Technologies Salland SEMATECH Semilab Shin-Etsu Polymer SigmaTech Soitec SUMCO SUSS Tamar Technology Tessera Texas Instruments Tezzaron TOK America TSMC Vertical Circuits WaferMasters Xilinx Zygo * partial list NA 3DS-IC Committee Report - September 2011

Leadership Committee Co-chairs Urmi Ray (Qualcomm) Sesh Ramaswami (Applied Materials) Chris Moore (Semilab) Rich Allen (SEMATECH) NA 3DS-IC Committee Report - September 2011

Organization Chart NA 3DS-IC Committee Wafer Bonded Stacks Task Force Chairs: Urmi Ray (Qualcomm) Sesh Ramaswami (Applied Materials) Chris Moore (Semilab) Rich Allen (SEMATECH) Wafer Bonded Stacks Task Force Leader: Rich Allen (SEMATECH) Thin Wafer Handling Task Force Leader: Urmi Ray (Qualcomm) Raghunandan Chaware (Xilinx) Inspection & Metrology Task Force Leader: Yi-Shao Lai (ASE) Curt Shannon (SigmaTech) David Read (NIST) Chris Moore (Semilab) Carrier Wafer Task Force To be chartered to develop standard(s) for dimensions and sizes for carrier wafers as well as edge trimming of the device wafer. NA 3DS-IC Committee Report - September 2011

Meeting Information Last meeting Next meeting July 12 for SEMICON West 2011 Meetings San Francisco, California Next meeting October 25 for NA Fall 2011 Meetings San Jose, California NA 3DS-IC Committee Report - September 2011

Task Force Overview 3DS-IC Wafer Bonded Stacks TF Approved late January 2011 Charter: The BWS Task Force will actively create and/or modify specifications that reflect bonded wafer stacks parameters and the wafer bonding process. Scope: Identify new wafer parameters that reflect adequate ranges for bonded wafer stacks Modify/create document to reflect adequate ranges for bonded wafer stacks Identify other SEMI standards that are adversely affected by BWS parameters Update referenced standards: create/modify standards to reflect BWS parameters NA 3DS-IC Committee Report - September 2011

Task Force Overview 3DS-IC Inspection & Metrology TF Approved late January 2011 Charter: Develop standards for metrology and inspection methods to be used in measuring the properties of TSV’s, bonded wafer stacks, and dies used in the 3DS-IC manufacturing process. Scope: Examples of needed standards include (but are not limited to): TSV physical properties (i.e., depth, top, bottom CD, side wall, etc.) Bonded wafer stack properties (i.e., overlay, bond inspection) Defect metrology Dies NA 3DS-IC Committee Report - September 2011

Task Force Overview 3DS-IC Thin Wafer Handling TF Approved late January 2011 Charter: Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro-pillar Grid array -MPGA) used in 3DS-IC high-volume manufacturing (HVM) Define thin wafer handling requirements including physical interfaces used in 3DS-IC manufacturing Define shipping requirements, including packaging, reliability, and other relevant criteria. This will also include MPGA ship/handle requirements NA 3DS-IC Committee Report - September 2011

Task Force Overview 3DS-IC Thin Wafer Handling TF (cont’d) Scope: Formulate a common set of requirements and prioritize critical areas for standardization, resulting in a short-list of required standards (inspection, shipping etc) in the topics listed below. Other topics may be added based on additional inputs Thin wafer and Die Shipping related activities: Examples: Shipping carriers for thin wafer (wafer cassette, box or frame), Shipping carrier for dies (MPGA), Reliability Test methods Transportation vibration testing Drop-shock Other – new tests? Thin wafer handling-related activities: Examples: Process and Metrology Tools and Test methods Whole wafer inspection for damage (crack, break etc)Macro level Damage to features – microbump, pad etc micro level Universal carrier concept Automation NA 3DS-IC Committee Report - September 2011

New SNARFs (Standards New Activity Report Form) Inspection & Metrology TF [Doc. 5269] New Standard: Guide for Terminology for Measured Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures [Doc. 5270] New Standard: Guide for Measuring Voids in Bonded Wafer Stacks Approved at SEMICON West 2011 NA 3DS-IC Committee Report - September 2011

Existing SNARFs Bonded Wafer Stacks TF Thin Wafer Handling TF [Doc. 5173] New Standard: Specification for Parameters for Bonded Wafer Stacks [Doc. 5174] New Standard: Specification for Identification and Marking for Bonded Wafer Stacks Thin Wafer Handling TF [Doc. 5175] New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers NA 3DS-IC Committee Report - September 2011

3DS-IC Meetings at SEMICON West 2011 July 12 Call for Participation: A working group will be formed to investigate the formation of a new task force that will develop standard(s) for dimensions and sizes for carrier wafers as well as edge trimming of the device wafer The output of this task force will be used in the development of the bonded wafer stacks specification by the Bonded Wafer Stacks TF Bonded Wafer Stacks TF Continued discussion and development of draft documents 5173 and 5174 (Doc. 5173) New Standard: Specification for Parameters for Bonded Wafer Stacks (Doc. 5174) New Standard: Specification for Identification and Marking for Bonded Wafer Stacks SNARF in development Specification for transport and storage containers for bonded wafer stacks NA 3DS-IC Committee Report - September 2011

3DS-IC Meetings at SEMICON West 2011 July 12 Inspection & Metrology TF New TF leaders: Yi-Shao Lai (ASE), Curt Shannon (SigmaTech), David Read (NIST) TF will develop a process flow map with known, as well as potential, areas for metrology Two SNARFs submitted to and approved by committee: (Doc. 5269) New Standard: Guide for Terminology for Measured Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures (Doc. 5270) New Standard: Guide for Measuring Voids in Bonded Wafer Stacks Discussed creating a reference standard on test and detection protocols for metrology tools to be used for round-robins Test protocol could be converted in to an AUX document NA 3DS-IC Committee Report - September 2011

3DS-IC Meetings at SEMICON West 2011 July 12 Thin Wafer Handling TF Continued discussion and development of draft document 5175 (Doc. 5175) New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers Activity will focus on: Shipping containers post-debond Transportation after dicing Containers that support tape frame Criteria for cleaning process (before as well as on mounted thin frame) Final packaging (structure for supporting wafers) Presentation from Shin-Etsu Polymer on Thin Wafer Shipper Solution Cushion film with coin stack carrier Reviewed standard on tape frame (SEMI G74) NA 3DS-IC Committee Report - September 2011

Since SEMICON West 2011… [1/2] Bonded Wafer Stacks TF Parameters for Bonded Wafer Stacks (#5173) Completed meetings: Aug 30 and Sep 14 Addressing both glass and silicon wafers Identifying single wafers and stacks Measuring bow, warp, etc. Wafer-to-wafer bond vs interconnect-to-interconnect bond Other standards to consider (e.g., M17, M20, M45, M59, M38, EA555-CEA, etc.) Discussed developing a guide for describing a 3DS-IC wafer stack Next meeting: Wed., Sept 28, 5-7 PM (Pacific), tentative Identification and Marking for Bonded Wafer Stacks (#5174) Next meeting: Wed., Sept 21, 5-7 PM (Pacific) NA 3DS-IC Committee Report - September 2011

Since SEMICON West 2011… [2/2] Inspection & Metrology TF Started work on Terminology for Measured Geometrical Parameters of TSVs (#5269), using SEMI P35 (Terminology for Microlithography Metrology) as a starting point (e.g., linewidth, pitch) Thin Wafer Handling TF Teleconference held on Aug 10 ASE presentation Thin Wafer Handling Requirements Achilles/SEP presentation 300 mm Coin Stack Type Shipping Container (SEMI G90) SEMATECH presentation Wafer Plan: Phase 1: bare silicon wafers thinned, on dicing frames, drop tested, shipped internationally (wafer supply > temporary bond > thinning > de-bond > drop-test/inspection > transportation/inspection) Phase 2: TSV/bumped wafers Next telecon: Wed., Sept 28, 5-6 PM (Pacific) NA 3DS-IC Committee Report - September 2011

Formation of the Taiwan 3DS-IC Technical Committee The International Standards Committee (ISC) approved a petition for the formation of the Taiwan 3DS-IC Standards Technical Committee at SEMICON West 2011 The Taiwan 3DS-IC committee plans to focus initially (and charter corresponding task forces) on testing and middle-end process. Testing To define a common testing standard and methodologies for probing test on heterogeneous chip stacking, passive interposer, intermediate, function tests , defective or the intermediate for the components and final 3DS-IC system/module. Middle-End Process Specifically for 3DS-IC middle-end processes involving shared activities between wafer foundry and OSATs, including embedded via protrusion and viaed wafer thinning. To define outgoing and incoming inspection items and metrologies for intermediate viaed wafers, in-process ESD criteria, in-process inspection items and metrologies in viaed wafer thinning process. Leaders Yi-Shao Lai (ASE), Wendy Chen (King Yuan Elec.), Tzu-Kun Ku (ITRI) NA 3DS-IC Committee Report - September 2011

NA 3DS-IC Fall 2011 Meeting Schedule [DRAFT] North America Standards Fall 2011 Meetings October 24-28, 2011 SEMI Headquarters 3081 Zanker Road San Jose, California / U.S.A. Tuesday, October 25 Inspection & Metrology TF (8:00 AM to 10:00 AM) Bonded Wafer Stacks TF (10:00 AM to 12:00 Noon) Thin Wafer Handling TF (1:00 PM to 3:00 PM) NA 3DS-IC Committee (3:00 PM to 5:00 PM) NA 3DS-IC Committee Report - September 2011

NA Standards Fall 2011 Meetings October 24-27 Sunday Monday Tuesday Wednesday Thursday Friday Saturday 23 24 25 26 27 28 29 NARSC EH&S Facilities & Gases HB-LED Information & Control MEMS/NEMS Metrics Photovoltaic Physical Interfaces & Carriers Silicon Wafer Traceability 3DS-IC Locations - SEMI - AMAT - Intel - Hynix NA 3DS-IC Committee Report - September 2011

Thank you! For more information, please visit the SEMI 3DS-IC Google Site: https://sites.google.com/a/semi.org/3dsic/ For more information or to participate in any NA 3DS-IC activities, please contact: Paul Trio SEMI North America Standards ptrio@semi.org NA 3DS-IC Committee Report - September 2011

Back-up NA 3DS-IC Committee Report - September 2011

New – SNARFs [5/5] Doc. 5270 – New Standard: Guide for Measuring Voids in Bonded Wafer Stacks Rationale This Guide will assist the user in selection and use of bond-void metrology tools based on their application and a protocol for performing bond-void measurements. New bonding processes and applications are sensitive to significantly smaller voids than bonding processes currently used for 3DS-IC package sealing. The Guide will compare detection, in bonded wafer pairs, of prefabricated voids in several oxide thicknesses, the void detection limits of a range of metrology tools and provide application recommendations. This activity will be executed in a planned 3DS-IC project at SEMATECH. The test results and analysis will create a fundamental study of oxide-bonded wafer pairs. Subsequently this study can assist producers and users of other wafer bonding processes to develop robust products and evaluations. Scope A number of technologies have been released to measure voids between bonded wafers. These technologies each have unique strengths and weaknesses. In this activity, we will compare the capabilities of these technologies and prepare a guide to the use and applicability of these tools for different bonding applications. Task Force Inspection & Metrology NA 3DS-IC Committee Report - September 2011

New – SNARFs [4/5] Doc. 5269 – New Standard: Guide for Terminology for Measured Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures Rationale Different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSV’s, such as pitch, top CD, top diameter, top area, depth, taper (or sidewall angle), bottom area, bottom CD, bottom diameter, and possibly others. However it is currently difficult to compare and/or correlate results from the various measurement technologies for various TSV dimensions. In some cases certain parameters may be described by similar names, but are actually different aspects of the TSV geometry. This standard will attempt to: a) Group the measurement results provided by the various technologies in such a way that correlations and comparisons are valid where possible; b) Clearly indicate the underlying issues in cases where valid comparisons and correlations are not geometrically valid. Scope Define terms currently used to describe TSV parameters which are not defined in current SEMI Standards, and list those that are already defined in current SEMI Standards. For each parameter (or group of parameters), the various technologies that are used will be listed, along with any limitations and/or issues and needs particular to that technology and to making valid comparisons to the others. Include applicable ranges for valid measurements where possible. Task Force Inspection & Metrology NA 3DS-IC Committee Report - September 2011

SNARFs [3/5] Doc. 5175 – New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers Rationale Current standards for wafer transport and storage containers (shipping boxes, FOUP, FOSBs) do not adequately address the reliable storage and transportation of thin wafers and dice on tape frame used in 3DS-IC manufacturing. Wafer thicknesses of 30-200um will need significant changes to the current design criteria of current wafer transport and storage containers. This will address robust handling and shipping of thin wafers, including changes in securing the wafers. New inspection processes will be addressed in the Inspection and Metrology TF. Scope Develop a thin wafer handling and shipping guide that will meet the needs of 3DS-IC manufacturing. Include: Standards for tape frame Standards for thin wafer on tape frame Requirements of capacity of containers Transportation/vibration and mechanical shock requirements Task Force Thin Wafer Handling TF NA 3DS-IC Committee Report - September 2011

SNARFs [2/5] Doc. 5174 – New Standard: Specification for Identification and Marking for Bonded Wafer Stacks Rationale Current wafer identification standards and wafer marking standards do not adequately address the needs of bonded wafer stacks. Location (e.g. backside near notch for SEMI T7) will be removed during backside thinning operations or edge-trim operations, or buried under an opaque layer of silicon and rendered un-readable by optical readers when bonded. Multiple wafer stacks will combine wafers with multiple process history, including tracking of temporary carrier wafers, and a standard needs to be developed to combine and track bonded wafer stacks with multiple wafer histories. Scope Develop an identification standard that will meet the needs of bonded wafer stacks. The initial focus will be temporary bonding and permanent bonding as driven by contributions. Task Force Bonded Wafer Stacks TF NA 3DS-IC Committee Report - September 2011

SNARFs [1/5] Doc. 5173 – New Standard: Specification for Parameters for Bonded Wafer Stacks Rationale Current wafer standards (SEMI M1) do not adequately address the needs of wafers used in bonded wafer stacks. Wafer thickness, edge bevel, notch, mass, bow/warp and diameters are changed when wafer stacks are bonded together, or wafer stacks bonded and thinned. These deviations from wafer parameters specified in SEMI M1 have numerous impacts in other equipment and hardware standards that reference SEMI M1, and drives a new standard to reflect wafer parameters associated with bonded and bonded/thinned wafer stacks. Scope Develop a standard that will meet the needs of bonded wafer stacks using temporary bonding to carrier wafers. This standard will reflect the new parameters (including thickness, edge bevel, notch, mass, bow/warp and diameters, etc.) associated with bonded wafer stacks including bonded and thinned stacks. This standard will include both Silicon and glass carrier wafers. Task Force Bonded Wafer Stacks TF NA 3DS-IC Committee Report - September 2011