Literature Review Demonstration of Integrated Micro-Electro-Mechanical Switch Circuits for VLSI Applications Fred Chen, Matthew Spencer, Rhesa Nathanael,

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Presentation transcript:

Literature Review Demonstration of Integrated Micro-Electro-Mechanical Switch Circuits for VLSI Applications Fred Chen, Matthew Spencer, Rhesa Nathanael, Chengcheng Wang, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu-Jae King Liu, Dejan Markovic, Vladimir Stojanovic, Elad Alon Massachusetts Institute of Technology, Cambridge, MA University of California, Berkeley, CA University of California, Los Angeles, CA ISSCC February, 2010 Kevin Dwan March 12, 2010 UCLA

Introduction How does the Micro-Electro-Mechanical (MEM) Device Work? Electro-static force actuates the Gate Can behave like a “pmos” or “nmos” Due to large size, requires large supply voltage (~10V) Can be monolithically integrated by using MEM process

MEM vs. CMOS What Advantages does this have over CMOS? CMOS circuits have lower boundary on energy efficiency due to sub-threshold leakage MEM devices minimize sub-threshold leakage to nearly ideal levels (~10x lower energy over CMOS) Are there any tradeoffs? Larger in area due to mechanical movement Mechanical delay is much higher than CMOS (can run up to ~100MHz)

MEM Circuit: Inverter & Carry-Generate Inverter/XOR Hysteretic switching Full rail output Enables cascades Carry-Generate 1 Mechanical Delay All inputs switch at once, due to large disparity between mechanical and electrical delay

MEM Circuit: Oscillator Mechanical Delay 28us Electrical Delay <100ns Can drive large loads Suitable for I/O

MEM Circuit: DAC Compute and communicate Can perform logic and drive loads

MEM Circuit: Latch Psuedo NMOS style Regenerative

MEM Circuit: DRAM Low leakage current is well suited for DRAM

Conclusion Demonstrates feasibility of computational and memory building blocks MEM Circuits can drive each other to form composable digital circuits Large disparity between Electrical and Mechanical delay requires circuit level re-architecting to capitalize on ideal Ion/Ioff characteristics Scaling, device reliability, and circuit design advancements are still needed Potential to become an attractive alternative to CMOS