1. The Inverter EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 731
The Inverter
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

2. Pass-Transistors NMOS based PMOS based
Need a circuit element which acts as a switch
When the control signal CLK is high, Vout=Vin
When the control signal CLK is low, Vout is open circuited
We can use NMOS or PMOS to implement it. For PMOS device, the polarity of CLK is reversed.
NMOS based
PMOS based

3. NMOS Pass Transistors Initially Vout=0. input=drain, output=source
When CLK=0, then Vgs=0. NMOS cut-off
When CLK=Vdd,
If Vin=Vdd (Vout=0 initially), Vgs>Vt, Vgs-Vt=Vdd-Vt<=Vds=Vdd, NMOS is in saturation region as a transient response and CL is charged.
When Vout reaches Vdd-Vt, Vgs=Vdd-(Vdd-Vt)=Vt. NMOS cut-off.
However, if Vout drops below Vdd-Vt, NMOS will be turned on again since Vgs>Vt.
Thus, NMOS transmits Vdd value but drops it by Vt.

4. NMOS Pass Transistors - II
If Vin=0 (and CLK=Vdd), source=input, drain=output
If Vout=Vdd-Vt (note that it is the maximum
value for Vout for the transistor to be on), Vgs=Vdd>Vt, Vds=Vdd-Vt=Vgs-Vt
The NMOS is on the boundary of linear region and saturation region
CL is discharged
As Vout approaches 0, the NMOS is linear region. Thus, Vout is completely discharged.
When Vout=0, Vds=0 and Ids=0, thus, the discharge is done.
NMOS pass transistor transmits a 0 voltage without any degradation

5. PMOS Pass Transistors Similar to NMOS pass transistor
Assume that initially Vout=0
When CLK=Vdd, PMOS cut-off
When CLK=0,
If Vin=Vdd, PMOS transmits a Vdd value without degradation
If Vin=0, PMOS transmits a 0 value with degradation, Vout=|Vt|

6. Transmission Gate
An NMOS transmits a 0 value without degradation while transmits a Vdd value with degradation
A PMOS transmits a Vdd value without degradation while transmits a 0 value with degradation
Use both in parallel, then can transmit both 0 and Vdd well.
CLK=0, both transistors cut-off
CLK=Vdd, both transistors are on. When Vin=Vdd, NMOS cut-off when Vout=Vdd-Vtn, but PMOS will drag Vout to Vdd. When Vin=0, PMOS cut-off when Vout=|Vtp|, but NMOS will drag Vout to 0.

7. Propagation Delay

8. Rising delay and Falling delay
Rising delay tr=time for the signal to change from 10% to 90% of Vdd
Falling delay tf=time for the signal to change from 90% to 10% of Vdd
Delay=time from input signal transition (50% Vdd) to output signal transition (50% Vdd).

9. Delay

10. Inverter falling-time

11. NMOS falling time S D V C in out L DD For NMOS
Vin=0, Vgsn=0<Vt, Vdsn=Vout=Vdd, NMOS is in cut-off region, X1
Vin=Vdd, instantaneously, Vgsn=Vdd>Vt,Vdsn=Vout=Vdd, Vgsn-Vtn=Vdd-Vtn<Vdd, NMOS is in saturation region, X2
The operating point follows the arrow to the origin. So Vout=0 at X3. V in
out C L DD S D

12. NMOS falling time tf1 tf2 When Vin=Vdd, instantaneously, Vgsn=Vdd
tf=tf1+tf2
tf1: time for the voltage on CL to switch from 0.9Vdd to Vgsn-Vtn=Vdd-Vtn
tf2: time for the voltage on CL to switch from Vdd-Vtn to 0.1Vdd
tf1
tf2

13. NMOS falling time Vgsn=Vdd Vdsn=Vout For tf1:
Integrate Vout from 0.9Vdd to Vdd-Vt
For tf2, we have

14. NMOS falling time
tf=tf1+tf2
Assume Vt=0.2Vdd

15. Rising time
Assume |Vtp|=0.2Vdd

16. Falling and Rising time
Assume Vtn=-Vtp, then we can show that
Thus, for equal rising and falling time, set
That is, Wp=2Wn since up=un/2

17. Power Dissipation

18. Where Does Power Go in CMOS?

19. Dynamic Power Dissipation
Vin
Vout C L
Vdd
Power = C
* V 2
* f L dd
Not a function of transistor sizes
Need to reduce C
, V
, and f
to reduce power. L dd

20. Dynamic Power
Dynamic power is due to charging/discharging load capacitor CL
In charging, CL is loaded with a charge CL Vdd which requires the energy of QVdd= CL Vdd2, and all the energy will be dissipated when discharging is done. Total power = CL Vdd2
If this is performed with frequency f, clearly, total power = CL Vdd2 f

21. Dynamic Power- II
If the waveform is not periodic, denote by P the probability of switching for the signal
The dynamic power is the most important power source
It is quadratically dependant on Vdd
It is proportional to the number of switching. We can slow down the clock not on the timing critical path to save power.
It is not dependent of the transistor itself but the load of the transistor.

22. Short Circuit Currents
Happens when both transistors are on.
If every switching is instantaneous, then no short circuits.
Longer delay -> larger short circuit power

23. Short-Circuit Currents

24. Leakage Sub-threshold current one of most compelling issues
in low-energy circuit design.

25. Subthreshold Leakage Component

26. Principles for Power Reduction
Prime choice: Reduce voltage
Recent years have seen an acceleration in supply voltage reduction
Design at very low voltages still open question (0.5V)
Reduce switching activity
Reduce physical capacitance

27. Impact of Technology Scaling

28. Goals of Technology Scaling
Make things cheaper:
Want to sell more functions (transistors) per chip for the same money
Build same products cheaper, sell the same part for less money
Price of a transistor has to be reduced
But also want to be faster, smaller, lower power

29. Scaling Goals of scaling the dimensions by 30%:
Reduce gate delay by 30%
Double transistor density
Die size used to increase by 14% per generation
Technology generation spans 2-3 years

30. EE141
Technology Scaling
Devices scale to smaller dimensions with advancing technology.
A scaling factor S describes the ratio of dimension between the old technology and the new technology. In practice, S= 30

31. Technology Scaling - II
EE141
Technology Scaling - II
In practice, it is not feasible to scale voltage since different ICs in the system may have different Vdd. This may require extremely complex additional circuits. We can only allow very few different levels of Vdd.
In technology scaling, we often have fixed voltage scaling model.
W,L,tox scales down by 1/S
Vdd, Vt unchanged
Area scales down by 1/S2
Cox scales up by S due to tox
Gate capacitance = CoxWL scales down by 1/S
scales up by S
Linear and saturation region current scales up by S
Current density scales up by S3
P=Vdd*I, power density scales up by S3
Power consumption is a major design issue 31

32. Summary Inverter Transmission gate Inverter delay Power
EE141
Summary
Inverter
Five regions
Transmission gate
Inverter delay
Power
Dynamic
Leakage
Short-circuit
Technology scaling 32