XC9500XL New 3.3v ISP CPLDs

XC9500XL Key Features High performance 36 to 288 macrocell densities tPD = 4ns, fSYS = 200MHz 36 to 288 macrocell densities Highest programming reliability 10,000 program/erase cycles Most complete IEEE 1149.1 JTAG support Space-efficient packaging, including chip scale pkg Industry’s first 0.35um Flash CPLD This lists the major, key features of the new 9500XL product family. Focus on the speed leadership. Also, point out that by using Flash technology, we can offer the best programming reliability (key for 50% of the CPLD applications today -- FIELD UPGRADES) as well as the lowest cost. CSP is leadership and only Xilinx has the 0.8mm ball-to-ball spacing. More on this in a later slide.

XC9500XL Architecture Embraces In-System Changes Advanced, 2nd Generation Pin-Locking Superior routability with speed Maximum Flexibility 54-input function block fan-in 90 p-terms per output 3 global, locally invertible clocks global set/reset pin p-term OE per macrocell clock enable The XC9500XL architecture is an enhancement of the popular XC9500 architecture, considered by many to be the most flexible architecture on the market-- for accommodating unexpected in-system changes! Pin-locking continues to improve, with the XL incorporating an even better pin-locking performance. This comes as a result of an enhanced interconnect, more inputs to the function block and significantly enhanced routing software. To make the 9500XL family THE most flexible (I.e., best at accommodating design changes while improving speed), we’ve provided this long list of industry leading architecture features. Especially key are the 54 function block inputs. The increase (with the 9500 having 36 inputs) provides more inputs to the function block, better overall utilization and better pin-locking. Only XILINX has 54 function block inputs! 5

XC9500XL System Features I/O Flexibility Input hysteresis on all pins 5v tolerant; direct interface to 3.3v & 2.5v Input hysteresis on all pins User programmable grounds Bus hold circuitry for simple bus interface Easy ATE integration for ISP & JTAG fast, concurrent programming times This list itemizes all the great system features that are available on the XC9500XL as is specifically targeted at meeting the system designer’s needs. Each feature is designed to help the actual application of incorporating a CPLD onto the system board.

New XC9500XL 3.3V Family XC9536XL XC9572XL XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 tPD (ns) 4 5 5 6 fSYSTEM 200 178 178 151 Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) 100TQ (81) 144TQ (117) 144CS (117) 144TQ (117) 208PQ (168) 352BG (192) The family is planned with 4 devices in the most popular macrocell densities. Note the full complement of pin-compatible package options. Each package has list in parenthesis the actual number of I/Os. Easy density migration is available for all like packages. This lowers the users risk when his/her design grows. World class speed spec’s reflect the key attribute of this new 3.3V ISP family. Only Xilinx offers a 4ns tpd and system cycle speeds of 200MHz. The family will become available starting 2H98, beginning with the XC95144XL. After that, the ‘72XL and ‘36XL will become available in end Q4C98. The 95288XL will be available in Q1C99. BGA CSP 9

Most Complete JTAG Testability IEEE Std 1149.1 boundary-scan testability & advanced system debug/diagnosis 8 instructions supported (incl. CLAMP) Full support on all family members Industry-standard ISP interface Complete 3rd party support The XC9500XL family has the most complete, industry-standard JTAG boundary-scan capabilities -- supporting an important capability for all new system designs. In addition to manufacturing test benefits, JTAG boundary-scan enhances development and debug as well, especially in complex, tightly packed systems. JTAG allows all internal nodes to be read out using only the 4 JTAG pins! The XC9500XL (along with XC9500) is the only CPLD family to support full JTAG boundary-scan in the whole CPLD family -- even lower density devices! The JTAG-based in-system programming (ISP) protocol allows compliance with emerging standards, such as the IEEE 1149.1 subcommittee formalizing a standard for ISP. 6

Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Xilinx has lead the industry again with the introduction of the small, space-efficient Chip Scale Package. The CSP solution is available on the 36XL/72XL and 144XL. The smaller package makes it ideal for applications that require programmable logic in the smallest footprint possible. Uses standard IR techniques for mounting to PC board

Productive Implementation Flow for CPLDs Simplified Project Management Implementation Templates for Speed & Density Push Button Design Flows USER BENEFITS Faster Clock Speeds Higher Device Utilization optimized logic/cm2 Industry’s Best Pin-Locking more design flexibility, less risk, lower cost The new v1.5 software provides CPLD designers with one of the industry best design flows available today. From the simple project manager, to the ready-built speed and density templates, and the push-button design flow manager, Xilinx CPLD software provides the designer with an excellent solution. These enhancement apply to both Foundation and Alliance software solutions from Xilinx.

Xilinx Lowering Cost Across The Supply Chain LEADING EDGE TECHNOLOGY STREAM-LINED OPERATIONS “MEMORY STYLE” MANUFACTURING 1st with Flash ISP Only true 0.35um Apply memory R&D advantages to CPLDs Long-term foundry agreements Stream-lined device/pkg offerings High volume packages 10ns slowest speed grade Off-shore sort, test and assembly Multi-site parallel test Fast time-to-market Xilinx has a very aggressive supply chain management program aimed at reducing cost, providing high volumes of product, in the right product options. Our Flash technology benefits are numerous and proven out by all the major memory vendors today. Operations are streamlined for efficiency and our manufacturing flow is set up very much like the way memories are handled today. All this supports our strategy of providing the most cost efficient CPLD in the industry. 9

XC9500XL The Complete CPLD Solution Product Life Cycle Support Flexible 3.3v ISP Architecture New Leadership Features Productive Software Lowest Cost Solution Today, Xilinx has moved from a supplier of CPLDs to a position of leadership in both 3.3v and 5v CPLDs. Lead by the XC9500XL 3.3v ISP CPLDs, and together with our software, Xilinx provides logic users the industry’s best SOLUTION today.