1. FLASH is the Future for CPLDs
XC New ISP Evolution
1st
Generation
ISP
FLASH for ISP:
- New Technology Driver
- 1/3 cell size of EEPROM
- Supported by Multiple Foundries
- excellent product availability
- Lower cost
FLASH
EEPROM
Early 80’s
Today
2000
Time
1993
1994
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1996
1997
1998
1999
2000
1000
3000
4000
5000
6000
7000
8000
Millions of US Dollars
FLASH
EEPROM
Source: Dataquest (May 1996)
Memory Shipments:
- Large FLASH growth to 2000
and beyond
- EEPROM flat M$
$8B
EEPROM technology, the present 10+ year old workhorse technology for most all CPLD products, is fast becoming a fully mature process making further density-based enhancements exponentially more difficult that previous densities (note the difficulty Altera has had releasing their MAX7128S product migration to production at only 0.5µ!). Add this to the present foundry plans of flat EEPROM capacity commitments and you can now can realize that EEPROM based products will not be optimized for future product performance, availability or cost. Bottom line, if you are not designing CPLDs in FLASH now, you’re falling farther and farther behind the curve.
FLASH, on the other hand, is clearly the technology that is driving all new silicon foundries and, as a result, will provide customers with the best performance, simplest technology migration paths to smaller geometries (down to .18µ), and excellent cost reductions. FLASH is new, has the attributes required to support a leadership product well into the early 2000s. That’s why Xilinx chose FLASH for the XC9500 and, as a result, provides that extra technology required to address the needs of the growing ISP CPLD marketplace. 1

2. Why Not EEPROM Technology?
FastFLASH Cell
Typical E2 CPLD Cell S1 3X
Routing
Switches
Source S2
Data S1 S3
Control
Word
Line
Since most all the other CPLD manufacturers build their devices in EEPROM, many of our customers will ask “Why didn’t you do what the other leading CPLD manufacturers are doing?”. As explained earlier, EEPROM is near the end of life cycle while FLASH is the chosen technology by AMD, Intel and most every new silicon foundry.
Key to this difference is cell size. Cell size comparisons show a FLASH CPLD cell 67% smaller than the same EEPROM CPLD cell. Since utilization with pin-locking is extremely critical for ISP CPLD users, this means Xilinx can put 3 times the number of routing switches in the same space as 1 EEPROM cell. Smaller is always better, making for significant improvements in pin-locking, performance and cost. And with FLASH comes the added benefit of improved endurance, or reprogramming.
Product benefits due to 67% smaller FLASH cell
More routing switches in the same area supports pinlocking
Lower parasitic capacitance improves performance
Long term cost improvements due to scalability 2

3. FLASH Technology Enables Rapid Die Size Reduction
1996
0.6µ
2Q98
0.5µ* 5v
2H98
0.35µ
3.3v
2H99
0.25µ
3.3v/2.5v
The simple geometry migration inherent with FLASH enables a direct path from the present 0.6µ directly to 0.5µ, quickly to 0.35µ, followed by 0.25µ by This results in significant performance improvements and cost reductions for our CPLD customers.
KEY POINT:
Note the die shrink from 0.6µ to 0.35µ, an excellent 65% reduction in die size!
1.0 .5
.35
.26
• 0.5µ transistor with 0.35µ interconnect 3

4. Xilinx - Leading Edge FLASH Technology for CPLDs1 2 V 1 2 V 5 V 5 V E / E E P R O M F l a s h E E P R O M F l a s h
XC9500
FastFLASH X i l i n x X C 7 3 _ _ _ _ L a t t i c e p L S I 1 / 2 _ _ i s p L S I 1 / 2 _ _ p L S I 3 i s p L S I 3 C y p r e s s C Y 7 C 3 F l a s h 3 7 _ _ _ _ ( M a x 5 )
Competitively, here is how the CPLD competitors stack up from a product family versus technology standpoint. Xilinx is the ONLY CPLD supplier with the NEW 5V ISP FLASH technology capability meaning that all present EEPROM suppliers will soon begin to struggle as they ramp up volumes on smaller geometry products with little or no increase in planned EEPROM foundry capacity. This is not the case with FLASH and as a result, Xilinx has laid the foundation better than any competitor for faster, denser, lower cost CPLDs, especially for ISP products.
Vantis M a c h 1 / 2 _ _ M a c h 3 / 4 _ _ A M D M a c h 4 3 5 M a c h 5* A l t e r a M a x 5 M a x 7
/S/A _ _ M a x 7 M a x 9 0A
* Also available in 3V EEPROM 4

5. FLASH Process Technology Roadmap.8 5v .6
Feature Size (µ) 5v 5v .4
3.3v
Xilinx will move to 0.35µ by 1Q98 for all products, both 5V and 3.3v. Additionally, we have an identical plan and path to lower voltages and geometries as our FPGA products.
For the 5v/0.35µ product noted in this slide and previous slides, the transistors are drawn to 0.5µ, with the interconnect dimensions being 0.35µ. .2
2.5v
1.8v
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Year 5