XILINX CPLDs The Total ISP Solution

Building CPLDs For Total Product Life Cycle Support XC9500/XL CPLDs Provides Total Solution Built for ISP & Superior Pin-Locking Uses Advanced Flash Technology Complete ISP/ATE Software Support Field Upgrades Proto- typing Product Life Cycle Manufacturing & Test

XC9500 Delivers Better ISP Solution Industry’s Best ISP with Pin-Locking Rapid prototyping and design fix implementation Streamlined manufacturing flows Flexibility to handle reprogramming during field upgrades 1. Reduced Time To Market The real benefits of pin-locking are shown above. Faster TTM (time-to-market), lower cost and lower risk all make for “real” customers benefits of pin-locking. As can be seen, pin-locking benefits help in every stage of the customer’s product life cycle: prototyping, manufacturing/test and field upgrades (something more and more customers are doing these days). The analogy is like the airbag in cars today. It’s advanced technology, can and does save your life (significant lower risk, cost), and something you want on every car you own now or will own in the future (lower risk). You may not every use it, but you always want it! Of course, pin-locking provides immediate benefits for the prototyping person, but as applications for ISP products expand, we need to make our customers WANT the best pin-locking so that if and when they need it (like during a last minute manufacturing design change or in field upgrades), Xilinx will be their only chose to provide it. Finally, no other CPLD competitor can provides these to customers the way Xilinx can. Customer Benefits 2. Reduced Costs 3. Reduced Risk

XC9500/XL CPLDs Key Features Flexible ISP architecture with superior pin-locking XC9500: 5v family XC9500XL: 3.3v family High performance: 4ns pin-to-pin (XL) Full IEEE 1149.1 JTAG 5v/3.3v/2.5v I/O compatibility Highest reprogramming reliability Space-efficient packaging Low cost

Xilinx CPLD Process Leadership Non-Volatile Year used in Year used in SPLD/CPLD Technology Memories SPLD/CPLD Pioneer Bipolar Fuse 1973 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5V EEPROM 1986 1991 Lattice ispLSI 5V FLASH 1990 1995 Xilinx XC9500 Xilinx is the world leader in FLASH process technology for CPLDs! The FastFLASH process uses the same device structures as the FLASH memories, which provides benefits in large economies of scale for R&D, and benefits in cost, speed, and foundry availability into the future. The process also allows intrinsic product benefits, including more routing switches in the same chip area, higher programming reliability (measured by endurance), and lower cell capacitance. As has been consistent since the 1970’s, PLD processes have historically leveraged the high-volume memory processes as process drivers, starting with the bipolar fuses. Going forward, FLASH process has become THE standard for non-volatile memory processes, and will become the standard for PLDs as well! 3.3V FLASH 1993 1998 Xilinx XC9500XL 7

FLASH Technology Enables Rapid Die Size Reduction

CPLD Price Leadership Without Compromises Flexible ISP tPD = 4ns (‘99); 2.5ns (‘02) Best Pin-Locking Industry Standard JTAG 2.5V (0.25u Flash) in 1999 $20 288 Macrocells $9 $ (unit price) $5.75 144 Macrocells Xilinx CPLDs will take full advantage of the leadership processing capabilities and small die sizes that result from our Flash process. The Flash process allows for constant die size reductions which, in turn, provide our customers with the best cost reduction path for the coming years. Three examples are shown to highlight the cost/price benefits from our Flash process migrations. Today, the 5v and 3.3v product are represented in this graph. From the year 2000 and on, prices represent the 3.3v (XL) and 2.5v (XV) products. Both the XL at 0.35 micron and the XV at 0.25 micron provide the optimum performance/price solution from the year 2000. Low pricing is key to our customer base but we give them the attractive price along with industry-leading product features like speed, pin-locking (pioneered and proven to be critical to ISP users by Xilinx) and full-up, industry standard JTAG. $3.95 $1.20 36 Macrocells $0.80 * Prices are based on 100Ku+, slowest speed grade, lowest cost package

Leadership Performance CPLDs fSYS (MHz) 300 300 0.18µ 250 250 0.25µ 200 200 0.35µ 150 3X improvement in 5 years 100 100 0.6µ/0.5µ New FLASH technology AND design enhancements are driving significant performance improvements, up to 300MHz by 2001. Fsys is a good measure of speed since it looks at how good your design is as well as how good your process technology is. Tpd is also an important metric. The present fastest Tpd is 5ns. This number will improve over the next 2-5 years, probably reaching 2.5ns to 3ns by 2001. However, Tpd is not only a measure of your design and technology, but it also includes other outside variables like package capacitance, bonding wire capacitance. So, Tpd’s will get faster as well as Fsys. 50 1996 1997 1998 1999 2000 2001/2 Year

Low Power CPLDs 5v Core Voltage 3.3v 2.5v 1.8v 1.0 .75 .5 .25 1995 Power (normalized) .5 3.3v 2.5v .25 1.8v With the advancement of technology comes the inherent advantage of power reduction. A 50% power reduction will be immediately realized when the 5V products move to 3.3V. When moving from 3.3v to 2.5v, users will again gain the benefit of approx.. 50% less power. This power benefit continues as the 2.5v users will reduce his/her power by approx.. 60%! All these power reductions come WITH a performance benefits as shows on the previous slide. These technology enhancements will truly benefit the CPLD user with BOTH HIGHER PERFORMANCE WITH LOWER POWER. 1995 1996 1997 1998 1999 2000 2002 Year * Same frequency and typical utilization

Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Uses standard IR techniques for mounting to PC board

New XC9500XL 3.3V Family XC9536XL XC9572XL XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 tPD (ns) 4 5 5 6 fSYSTEM 200 178 178 151 Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) 100TQ (81) 144TQ (117) 144CS (117) 144TQ (117) 208PQ (168) 352BG (192) The family is planned with 6 devices in the most popular macrocell densities. Note the full complement of pin-compatible package options. The family will become available starting 2H98, beginning with the XC95144XL. After that, the ‘72XL and ‘36XL will become available. BGA CSP 9

XC9500 5V Family XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 tPD (ns) 5 7.5 7.5 7.5 10 15 fSYSTEM 100 83 83 83 67 56 Max. User I/Os 34 72 108 133 166 192 Packages (Max. User I/Os) 44VQ (34) 48 CSP(34) 44PC (34) 84PC (64) 100TQ (72) 100PQ (72) 84PC (69) 100TQ (81) 100PQ (81) 160PQ (108) 160PQ (133) 208HQ (168) 352BG (192) 208HQ (166) 352BG (166)) The family as it is today. Many customers are still learning about the Xilinx XC9500 and this foil provides them all the necessary basic information to become familiar with the family quickly. Note: Based on refocused priorities toward 0.5µ and 0.35µ products, the XC95180 is not longer part of the family. All XC95180 designs are easily accommodated by the XC95216, thus simplifying the number of devices and the overall density message without leaving a density gap for our customers.

Productive Implementation Flow for CPLDs Simplified Project Management Implementation Templates for Speed & Density Push Button Design Flows USER BENEFITS Faster Clock Speeds Higher Device Utilization optimized logic/cm2 Industry’s Best Pin-Locking more design flexibility, less risk, lower cost

What’s New In V1.5 CPLDs Evolutionary Logic Algorithms for XC9500 5V CPLDs higher clock frequencies, improved density & faster runtimes Full Support of XC9500XL 3.3V CPLDs Includes “Advance” speed grades for fastest XC9500XL devices Improved Timing Driven CPLD Fitting JTAG Programmer now supports: XC9500/XL CPLDs, Virtex, XC4000E/X/XL, XC5200, SPARTAN/XL FPGAs XC9500/9500XL support in LogiBLOX AllianceCORE CPLD based IP

XILINX CPLDs The total ISP solution Complete support of customer’s Product Life Cycle Industry’s best pin-locking CPLD at lowest price Multiple software solutions to choose from Based on leadership FLASH technology CPLD users are all going to ISP and Xilinx will be “driving” this ISP evolution process with the XC9500. It offers the industry’s best product life cycle support, pin-locking, architecture and software to enable this evolution to take place. No other competitor offers this complete of a solution to the CPLD market. And now, with this roadmap, CPLD users can now see the Xilinx commitment to providing the next generations of CPLD products, all which will be design to fit the users needs.

CPLD Roadmap Appendix

CPLD Product Roadmap 1996 1997 1998 1999 2000 2001 2002 Advanced Architecture 0.18µ/6LM/1.8V K2 0.25µ/5LM/2.5V XC9500XV 0.35µ/4LM/3.3V XC9500XL Long Term Availability 0.5µ/3LM/5V* XC9500 Xilinx is presently shrinking the existing XC9500 0.6µ/5v CMOS FLASH family to 0.35µ/5v. Internally, this upgrade is a 0.5µ/5v device using 0.35µ interconnect. This provides a smaller die size and a performance advantage. Concurrently, Xilinx is developing a true 0.35µ/3.3v version of the present XC9500 family. Presently designated as the XC9X00XL, this new family will use all the advantages of small geometry FLASH to provide the 3.3V ISP user with the flexibility of CPLDs with much higher performance, lower power and lower cost. Additionally, R & D work has already begun on a 2.5V/.25µ ISP family which will complement the previous Xilinx ISP products. 0.6µ/2LM/5V XC9500 1996 1997 1998 1999 2000 2001 2002 * 0.5µ transistor with 0.35µ interconnect

CPLD Family Overview Fastest Speed Family Process Voltage tPD fSYS I/Os XC9500 0.6µ 5V 5ns 100 MHz Mixed system* capability XC9500 0.5µ/0.35µ 5V 5ns 125 MHz Mixed system* capability XC9500XL 0.35µ 3.3V 4ns 200 MHz 5 volt compatible** I/Os XC9500XVA 0.25µ 2.5V <4ns 225+ MHz 3.3 volt I/O, 5 volt compatible** Xilinx will aggressively push both the technology and design aspects so that leading-edge performance levels are met. Tpd improvements, driven by not only design but physical on-and-off chip limitations, will continue to improve. By the 0.25µ time, speeds will be less than 4 ns. Fsys, the maximum internal frequency, will show significant speed enhancements, from 100MHz today to greater than 200MHz in only a few years. This speed improvement is driven by both architectural enhancements and technology advancements. The I/Os will be extremely flexible and operate exactly as our FPGAs will. *Can safely drive 3 volt devices when in “TTL mode” **Can be safely driven with 5 volt logic and can drive TTL levels