Transistors (MOSFETs) MOS Field-Effect Transistors (MOSFETs) Sedra 1

The Analog Design- Example The Specification frequency = 100 Mhz gain = 20 VDD = 3.3V Ipol = 0.66 mA sedr42021_0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

The Analog Design- Example The Development Wn1=Wn2= 100 mm Ln1= Ln2= 0.4 mm Rcarga= 2.5 kW Rdes= 8.7 kW Cdes = 1.82 pF sedr42021_0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

Transistors in parallel The Analog Design- Example The Layout Implementation sedr42021_0401a.jpg Transistors in parallel Microelectronic Circuits - Fifth Edition Sedra/Smith

The Digital Design- Example The Specification -- Architecture Body ARCHITECTURE CountArch OF count_n_usp IS BEGIN PROCESS (clock) VARIABLE count : INTEGER RANGE 0 TO 255; IF (reset= '1') THEN count:=0; ELSE IF ( clock'event and clock= '1') THEN IF enable = '1' THEN IF updown = '1' THEN IF count = 217 THEN count := 0; ELSE count := count + 1; END IF; IF count = 0 THEN count := 217; ELSE count := count - 1; <= count AFTER 10 ns; END PROCESS; End CountArch; ENTITY count_n_usp IS PORT ( clock : IN BIT; enable: IN BIT; updown : IN BIT; reset : IN BIT; qa : OUT INTEGER RANGE 0 TO 255 ); END count_n_usp; sedr42021_0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

The Digital Design- Example The Development Schematics Simulation sedr42021_0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

The Digital Design- Example The Layout Implementation Standard-cells sedr42021_0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

The Digital Design- Example The Standard-cell sedr42021_0401a.jpg Transistors Microelectronic Circuits - Fifth Edition Sedra/Smith

The Structure (transistor) sedr42021_0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

The Structure sedr42021_0401a.jpg Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Microelectronic Circuits - Fifth Edition Sedra/Smith

Creating the Channel (VDS=0V) sedr42021_0402.jpg Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate. Microelectronic Circuits - Fifth Edition Sedra/Smith

Applying Small VDS sedr42021_0403.jpg Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity). Microelectronic Circuits - Fifth Edition Sedra/Smith

IDS-VDS Characteristics sedr42021_0404.jpg Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS. Microelectronic Circuits - Fifth Edition Sedra/Smith

Increasing VDS sedr42021_0405.jpg Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt. Microelectronic Circuits - Fifth Edition Sedra/Smith

More IDS-VDS Characteristics sedr42021_0406.jpg Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt. Microelectronic Circuits - Fifth Edition Sedra/Smith

Channel Depth Reduction at Drain sedr42021_0407.jpg Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape. Microelectronic Circuits - Fifth Edition Sedra/Smith

MOSFET Symbols sedr42021_0410a.jpg Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant. Microelectronic Circuits - Fifth Edition Sedra/Smith

n-channel MOSFET operating regions sedr42021_0411a.jpg Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2. Microelectronic Circuits - Fifth Edition Sedra/Smith

IDS-VDS –VGS Equations From Rabaey 2003

IDS-VGS –(Fixed VDS) sedr42021_0412.jpg Figure 4.12 The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, k’n W/L = 1.0 mA/V2). Microelectronic Circuits - Fifth Edition Sedra/Smith

Ideal Large Signal Equivalent Circuit in Saturation sedr42021_0413.jpg Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region. Microelectronic Circuits - Fifth Edition Sedra/Smith

nMOS Relative Voltage Levels sedr42021_0414.jpg Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in the saturation region. Microelectronic Circuits - Fifth Edition Sedra/Smith

Channel Length Modulation After Saturation sedr42021_0415.jpg Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL). Microelectronic Circuits - Fifth Edition Sedra/Smith

Non-ideal Large Signal Equivalent Circuit in Saturation sedr42021_0417.jpg Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22). Microelectronic Circuits - Fifth Edition Sedra/Smith

p-channel MOSFET VD smaller than +5V sedr42021_0418a.jpg Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal. Microelectronic Circuits - Fifth Edition Sedra/Smith

p-channel IDS-VDS -VGS Characteristics -2.5 -2 -1.5 -1 -0.5 -0.8 -0.6 -0.4 -0.2 x 10 -4 V DS (V) -I D (A) VGS = -1.0V VGS = -1.5V DS Or I VGS = -2.0V Assume all variables negative! VGS = -2.5V

pMOS Relative Voltage Levels sedr42021_0419.jpg Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region and in the saturation region. Microelectronic Circuits - Fifth Edition Sedra/Smith

Non-ideal Large Signal Equivalent Circuit in Saturation sedr42021_tb0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

The Threshold Voltage and the Body Effect Threshold voltage for VSB=0V Body Effect Parameter Surface Potential Silicon Permittivity Substrate Doping Concentration