1. 6.3.3 Short Channel Effects
When the channel length is small (less than 1m), high field effect must be considered.
For Si, a better approximation of field-dependent carrier velocity is
where  is low field mobility, vs is the constant saturation velocity for high fields

2. Consider the p+-n-p+ BJT from problem 7.7a
6.4 Metal-Insulator-Semiconductor FET (MISFET, IGFET)
Consider the p+-n-p+ BJT from problem 7.7a I p+ n p+ + E B C V −
IB = 0
IC = I0
without the Base current, we cannot inject holes at the Emitter junction

3. G D S Now instead of a base connection, let us add an insulated gate.p+ n p+ + E B C V −

4. 6.4 Metal-Insulator-Semiconductor FET (MISFET, IGFET)
MetalGate electrode; metal or heavily doped polysilicon
InsulatorSilicon dioxide SiO2
SemiconductorSilicon
Metal-oxide-semiconductor FET (MOSFET)
In a MOSFET, the channel current is controlled by a voltage applied at a gate electrode
that is isolated from the channel by an insulator (oxide)
In the n-channel MOSFET shown in Fig. 6-10, with no gate voltage applied
No current flows from Drain to Source
Two back-to-back p-n junctions, large electron energy barrier
Enhancement mode device: Normally off. VG must be applied to form a conducting channel
and to turn on the device
Depletion mode device: Normally on. VG must be applied deplete the conducting channel
which exists at equilibrium and to turn off the device

5. When a positive Gate Voltage VG is applied
Positive charges are deposited on the gate metal
Negative charges are induced electrostatically in the underlying Si
When VG>VT, an “inverted” conducting n-channel is formed between S(n+) and D (n+) through
which a large current can flow. The FET is ON.
VT is the threshold voltage, the minimum gate
voltage required to induce the conducting channel
With VG>VT, the conductance of the channel can
be modulated by varying VG

6. Figure 6—10
An enhancement-type n-channel MOSFET: (a) isometric view of device and equilibrium band diagram along channel; (b) drain current—voltage output characteristics as a function of gate voltage.

7. Figure 6—11
n-channel MOSFET cross-sections under different operating conditions: (a) linear region for VG > VT and VD < (VG - VT); (b) onset of saturation at pinch-off, VG > VT and VD = (VG - VT); (c) strong saturation, VG > VT and VD > (VG - VT ).

8. Now instead of a n-type material sandwiched between two p+ materials, let us put another p-type material. G I S D p+ p p+ + V −
Depletion Mode

9. Figure 6—26
Schematic view of the n-channel region of a MOS transistor under bias below pinch-off, and the variation of voltage Vx along the conducting channel.

10. Figure 6—27
Drain current–voltage characteristics for enhancement transistors: (a) for n-channel VD, VG, VT, and ID are positive; (b) for p-channel all these quantities are negative.

11. Figure 6—32
Experimental output characteristics of n-channel and p-channel MOSFETs with 0.1 mm channel lengths. The curves exhibit almost equal spacing, indicating a linear dependence of ID on VG, rather than a quadratic dependence. We also see that ID is not constant but increases somewhat with VD in the saturation region. The p-channel devices have lower currents because hole mobilities are lower than electron mobilities.

12. Figure 6—33
Cross section of a MOSFET. This high resolution transmission electron micrograph of a silicon Metal–Oxide Semiconductor Field Effect Transistor shows the silicon channel and metal gate separated by a thin (40Å, 4nm) silicon–dioxide insulator. The inset shows a magnified view of the three regions, in which individual rows of atoms in the crystalline silicon can be distinguished. (Photograph courtesy of AT&T Bell Laboratories.)

13. Figure 6—34
Thin oxide in the gate region and thick oxide in the field between transistors for VT control (not to scale).

14. Figure 6—35
Adjustment of VT in a p-channel transistor by boron implantation: (a) boron ions are implanted through the thin gate oxide but are absorbed within the thick oxide regions; (b) variation of implanted boron concentration in the gate region — here the peak of the boron distribution lies just below the Si surface.

15. Figure 6—36
Typical variation of VT for a p-channel device with increased implanted boron dose. The originally enhancement p-channel transistor becomes a depletion-mode device (VT > 0) by sufficient B implantation.

16. Figure 6—39
Equivalent circuit of a MOSFET, showing the passive capacitive and resistive components. The gate capacitance Ci is the sum of the distributed capacitances from the gate to the source-end of the channel (CGS) and the drain-end (CGD). In addition, we have an overlap capacitance (where the gate electrode overlaps the source/drain junctions) from the gate-to-source (COS) and gate-to-drain (COD). COD is also known as the Miller overlap capacitance. We also have p-n junction depletion capacitances associated with the source (CJS) and drain (CJD). The parasitic resistances include the source/drain series resistances (RS and RD), and the resistances in the substrate between the bulk contact and the source and drain (RBS and RBD). The drain current can be modeled as a (gate) voltage-controlled constant-current source.

17. Figure 6—41
Short channel effects in MOSFETs. As MOSFETs are scaled down, potential problems due to short channel effects include hot carrier generation (electron-hole pair creation) in the pinch-off region, punchthrough breakdown between source and drain, and thin gate oxide breakdown.