Presentation is loading. Please wait.

Presentation is loading. Please wait.

Field Effect Transistors

Similar presentations


Presentation on theme: "Field Effect Transistors"— Presentation transcript:

1 Field Effect Transistors
Slides taken from: A.R. Hambley, Electronics, © Prentice Hall, 2/e, 2000 A. Sedra and K.C. Smith, Microelectronic Circuits, © Oxford University Press, 4/e, 1999

2 Overview (1) Types of FET p-channel JFET n-channel enhancement
MOSFET p-channel n-channel enhancement depletion

3 Overview (2) FET characteristics and modes of operation
Analysis and Design of FET Amplifiers bias operating point (DC analysis) small signal model (AC analysis)

4 Enhancement mode n-MOSFET
Figure 5.1 n-Channel enhancement MOSFET showing channel length L and channel width W.

5 Figure 5.2 Circuit symbol for an enhancement-mode n-channel MOSFET.
Enhancement mode n-MOSFET Figure 5.2 Circuit symbol for an enhancement-mode n-channel MOSFET.

6 nMOS operation modes (1)
Fig An NMOS transistor with vGS < Vt The device acts as an open circuit.

7 nMOS operation modes (2)
Fig An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the depletion region is not shown (for simplicity).

8 nMOS operation modes (3)
Fig Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

9 Derivation of the iD vs. vDS characteristic
Fig Derivation of the iD - vDS characteristic of the NMOS transistor.

10 Derivation of the iD vs. vDS characteristic

11 nMOS equations (1)

12 nMOS equations (2)

13 nMOS characteristics Source: Kang, Leblebici, CMOS Digital Integrated Circuits, 3/e, McGraw-Hill

14 nMOS output characteristics
Fig (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iD - vDS characteristics for a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2.

15 Zooming in the output characteristics
Fig The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

16 nMOS in saturation: iD vs. vGS
Fig The iD - vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V and k’n(W/L) = 0.5 mA/V2).

17 channel length modulation
Fig Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by L).

18 Effect of channel length modulation
Fig Effect of vDS on iD in the saturation region. The MOSFET parameter VA is typically in the range of 30 to 200 V.

19 The device’s figure of merit

20 The MOSFET as an amplifier
Fig Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.

21 Small signal analysis (AC)
Fig Small-signal operation of the enhancement MOSFET amplifier.

22 Total component analysis (DC + AC)
Fig Total instantaneous voltages vGS and vD.

23 Total component analysis

24 Total component analysis

25 Small signal models Fig Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation effect); and (b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.

26 Figure 5.24 Determination of gm and ro

27 Load Line Analysis Example (1)

28 Load Line Analysis Example (2)

29 Load Line Analysis Example (3)

30 Practical Bias Circuits (1) (DC operating point)

31 Practical Bias Circuits (2) (DC operating point)

32 Practical Bias Circuits (3): Load Line

33 Practical Bias Circuits (4): Load Line

34 Practical Bias Circuits (4) (DC operating point)

35 Practical Bias Circuits (5) (DC operating point)

36 Practical Bias Circuits (5) (DC operating point)

37 An Alternative Bias Circuit (6) (DC operating point)

38 Common Source (CS) Amplifier with Degeneration (1)

39 Common Source (CS) Amplifier with Degeneration (2)

40 Common Source (CS) Amplifier w/o degeneration (1)

41 Common Source (CS) Amplifier w/o degeneration (2)

42 Common Drain (CD) Amplifier

43 Common Drain (CD) Amplifier (2)

44 Common Gate (CG) Amplifier (1)

45 Common Gate (CG) Amplifier (2)

46 Common Gate (CG) Amplifier (3)

47 n-MOSFET current mirror

48 MOSFET current mirror characteristic
Fig Output characteristic of the current source in Fig and the current mirror for the case Q2 is matched to Q1.

49 p-MOSFET current mirror

50 Common source amplifier
Fig The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to determine the transfer characteristic; and transfer characteristic.

51 CS amplifier (small signal analysis)
Q2 is modeled as usual by a current source I2 with in parallel ro2. However I2 is a DC current source so from a small signal pespective It is an open !!!

52 Body effect (1)

53 Body effect (2)

54 Body effect (3)

55 Body effect (4)

56 Common gate amplifier Fig The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).

57 CG amplifier (small signal analysis)

58 CG amplifier (small signal analysis)

59 Common drain amplifier
Fig The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.

60 CD amplifier (small signal analysis)

61 CD amplifier (small signal analysis)

62 Junction FET (n-channel)
Figure 5.38 n-Channel JFET.

63 (Note: The two gate regions of each FET are connected to each other.)
JFET for vDS=0 (n-channel) Figure 5.39 The nonconductive depletion region becomes thicker with increased reverse bias. (Note: The two gate regions of each FET are connected to each other.)

64 Figure 5.42 n-Channel FET for vGS = 0.
JFET for vGS=0 (n-channel) Figure 5.42 n-Channel FET for vGS = 0.

65 JFET for vGS=0 (n-channel)
Figure 5.41 Drain current versus drain-to-source voltage for zero gate-to-source voltage.

66 Figure 5.43 Typical drain characteristics of an n-channel JFET.
n-channel JFET: output characteristics Figure 5.43 Typical drain characteristics of an n-channel JFET.

67 n channel JFET: iD vs. vGS

68 Breakdown Figure 5.44 If vDG exceeds the breakdown voltage VB, drain current increases rapidly.

69 Figure 5.46 n-Channel depletion MOSFET.
Depletion mode n-MOSFET Figure 5.46 n-Channel depletion MOSFET.

70 Depletion n-MOSFET characteristics
Fig The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic in saturation.

71 n-channel FET Figure 5.47 Drain current versus vGS in the saturation region for n-channel devices.

72 p-channel FET Figure 5.48 p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices, except for the directions of the arrowheads.

73 iD vs. vGS for the various FET
Figure 5.49 Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal for n-channel devices and out of the drain for p-channel devices.

74 p-FET equations

75 p-FET output characteristics


Download ppt "Field Effect Transistors"

Similar presentations


Ads by Google