1. Recall Lecture 17 MOSFET DC Analysis
Using GS (SG) Loop to calculate VGS
Remember that there is NO gate current!
Assume in saturation
Calculate ID using saturation equation
Find VDS (for NMOS) or VSD (for PMOS)
Using DS (SD) loop
Calculate VDS sat or VSD sat
Confirm that VDS > VDS sat or VSD > VSD sat
Confirm your assumption!

2. Application of mosfets

3. NOR gate response The NAND gate response 5
Digital Logic Gates
NOR gate
NAND gate
NOR gate response
The NAND gate response
High 5
Low

4. CHAPTER 7
Basic FET Amplifiers

5. For linear amplifier function, FET is normally biased in the saturation region.

6. AC PARAMETERS
where

7. The MOSFET Amplifier - COMMON SOURCE
The output is measured at the drain terminal
The gain is negative value
Three types of common source
source grounded
with source resistor, RS
with bypass capacitor, CS

8. Common Source - Source Grounded
A Basic Common-Source Configuration:
Assume that the transistor is biased in the saturation region by resistors R1 and R2, and the signal frequency is sufficiently large for the coupling capacitor to act essentially as a short circuit.

9. EXAMPLE VDD = 5V The transistor parameters are:
Rsi
RD = 10 k
0.5 k
520 k
320 k
The transistor parameters are:
VTN = 0.8V, Kn = 0.2mA/V2 and  = 0.
ID = mA
gm = mA/V

10. (replace into equation from step 2)
RTH k
0.5 k
RD = 10 k
0.442 vgs
The output resistance, Ro = RD
The output voltage:
vo = - gmvgs (Rout) = - gmvgs (10) = vgs
The gate-to-source voltage: , Ri = RTH
vgs = [198.1 / ( )] = vi
(replace into equation from step 2)
So the small-signal voltage gain:
Av = vo / vi =

11. Type 2: With Source Resistor, RS
VTN = 1V, Kn = 1.0mA / V

12. Assume transistor in saturation
Perform DC analysis
Assume transistor in saturation
VG = ( 200 / 300 ) x 3 = 2 V
Hence, KVL at GS Loop:
VGS + IDRS – VTH = 0
VGS = 2 – 3ID
KVL at DS loop
VDS + 10 ID + 3ID – 3 = 0
VDS = ID
Assume biased in saturation mode:
Hence, ID = 1.0 (2 – 3ID - 1 )2 = 1.0 (1 – 3ID )2
 9 ID2 – 7 ID + 1 = 0
VTN = 1V, Kn = 1.0 mA / V

13. ID = mA
ID = 0.19 mA
VGS = 2 – 3ID = < VTN
VGS = 2 – 3ID = 1.43 V > VTN
MOSFET is OFF OK
Not OK
VDS = ID = 0.53 V
VDS sat = VGS - VTN = 1.43 – 1.0 = 0.43 V
0.53 V > 0.43 V
Transistor in saturation
Assumption is correct!

14. v’ = vgs + gmvgs RS  v’ = vgs(1 + 2.616) = 3.616 vgs -
RTH
RD = 10 k
66.67 k
RS = 3 k
gm = mA/V
The output resistance, Ro = RD
The output voltage:
Find v’
v’ = vgs + gmvgs RS  v’ = vgs( ) = vgs
vo = - gmvgsRD = ( vgs) (10) = vgs

15. + V’ -
RTH
RD = 10 k
66.67 k
RS = 3 k
3. Find v’ in terms of vi : using voltage divider
v’ = [RTH / (Rsi + RTH)] vi
But in this circuit, Rsi = 0 so, v’ = vi = vgs
4. Go back to vo equation:
vo = vgs
vo = ( vi / 3.616)
AV= vo / vi =

16. Type 3: With Source Bypass Capacitor, CS
Circuit with Source Bypass Capacitor
An source bypass capacitor can be used to effectively create a short circuit path during ac analysis hence avoiding the effect RS
CS becomes a short circuit path – bypass RS; hence similar to Type 1

17. IQ = 0.5 mA hence, ID = 0.5 mA gm = 2 Kn ID = 1.414 mA/V ro =  RG
RD = 7 k
1.414 vgs

18. The output resistance, Rout = RD
The output voltage:
vo = - gmvgs (RD) = (7) vgs = vgs
3. The gate-to-source voltage:
vgs = vi  in parallel ( no need voltage divider)
4. So the small-signal voltage gain:
Av = vo / vi =

19. The MOSFET Amplifier - COMMON DRAIN
The output is measured at the source terminal
The gain is positive value

20. ID = 8 mA , Kn = 4 mA /V2 gm = 2 Kn ID = 11.3 mA/V 0.5 k 0.5 k RTH

21. gm = 2 Kn ID = 11.3 mA/V + v’ -
The output resistance:
The output voltage
v’ in terms of vi:
KVL at supermesh:
The voltage gain
Ro = ro || Rs
vo = gmvgs (ro  RS) = 11.3 vgs ( ) = 8 vgs
v’ = (RTH / RTH + RSi) vi = vi
vgs + gmvgs (ro  RS) – v’ = 0
v’ = vgs + 8 vgs  vgs = v’ / [1+8] = vi / 9 = vi
(replace into equation from step 2)
Av = vo / vi = 0.888

22. Output Resistance for Common Drain+ - Vx Ix
ro|| Rs = k
vgs in terms of Vx where vgs = -Vx
- Vx gmvgs Ix = 0
0.708
- Vx gmVx Ix = 0
0.708
Vx – 11.3 Vx + Ix = 0
Ix = Vx
0.079 k