1. Recall Last Lecture The MOSFET has only one current, ID
Operation of MOSFET
NMOS and PMOS
For NMOS,
VGS > VTN
VDS sat = VGS – VTN
For PMOS
VSG > |VTP|
VSD sat = VSG + VTP

2. ID versus VDS (NMOS) or ID versus VSD (PMOS)

3. PMOS NMOS VTP is NEGATIVE VTN is POSITIVE VSG > |VTP| to turn on
Triode/non-saturation region
Saturation region
VSDsat = VSG + VTP
NMOS
VTN is POSITIVE
VGS > VTN to turn on
Triode/non-saturation region
Saturation region
VDSsat = VGS - VTN

4. DC analysis of FET

5. MOSFET DC Circuit Analysis - NMOS
The source terminal is at ground and common to both input and output portions of the circuit.
The CC acts as an open circuit to dc but it allows the signal voltage to the gate of the MOSFET.
In the DC equivalent circuit, the gate current into the transistor is zero, the voltage at the gate is given by a voltage divider principle:
VG = VTH = R2 VDD
R1 + R2

6. MOSFET DC Circuit Analysis - NMOS
Calculate the value of VGS
Assume the transistor is biased in the saturation region, the drain current:
Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD - IDRD
Calculate VDSsat = VGS - VTN
Confirm your assumption:
If VDS > VDS(sat) = VGS – VTN, then the transistor is biased in the saturation region. If VDS < VDS(sat), then the transistor is biased in the non-saturation region.

7. EXAMPLE:
Assume the transistor is biased in the saturation region, the drain current:
Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD – IDRD = 3 V
Calculate the drain current and drain to source voltage of a common source circuit with an n-channel enhancement mode MOSFET. Assume that R1 = 30 k, R2 = 20 k, RD = 20 k, VDD = 5V, VTN = 1V and Kn = 0.1 mA/V2
Calculate the value of VGS
Calculate VDSsat = VGS – VTN = 2 – 1 = 1V
Confirm your assumption: VDS > VDSsat, our assumption that the transistor is in saturation region is correct

8. EXAMPLE The transistor has parameters VTN = 2V and Kn = 0.25mA/V2.
Find ID and VDS
VDD = 10V
RD = 10k
R1 = 280k
R2 = 160k

9. Solution Calculate the value of VGS
Assume the transistor is biased in the saturation region, the drain current:
Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD – IDRD = 3.31 V
Calculate the value of VGS
Calculate VDSsat = VGS – VTN = – 2 = V
Confirm your assumption: VDS > VDSsat, our assumption that the transistor is in saturation region is correct
Answer: ID = mA and VDS = 3.31 V
KVL at GS loop: VGS – VTH + 0 = 0  VGS = VTH

10. MOSFET DC Circuit Analysis - PMOS
Different notation:
VSG and VSD
Threshold Voltage = - VTP + -
VSD ID
VDD R1 R2 RD
VSG

11. Calculate the drain current and source to drain voltage of a common source circuit with an p-channel enhancement mode MOSFET.
Also find the power dissipation. Assume that, VTP = -1.1V and Kp = 0.3 mA/V2
50 k
7.5 k 5V
Calculate the value of VSG
VTH = 2.5 V
Use KVL at SG loop:
VSG – 5 = 0
VSG = 5 – 2.5 = 2.5 V
Assume the transistor is biased in the saturation region, the drain current:
Use KVL at SD loop
IDRD + VSD – VDD = 0
VSD = VDD – IDRD = V
Calculate VSDsat = VSG +VTP = 2.5 – 1.1 = 1.4 V
Confirm your assumption: VSD < VSD sat , so our assumption that the transistor is in saturation region is incorrect

12. That means our transistor is in non-saturation mode: Go back to step 2
ID = ( 1.4 ) (5 – IDRD) – (5 – IDRD)2
ID = (5 – 7.5 ID) – ( ID)2
ID = – 21 ID – (25 – 75ID ID2)
ID = – 21 ID ID – ID2
ID = 4.2 – 6.3 ID – ID – ID2
ID2 – 15.2 ID = 0
ID = mA
ID = mA

13. ID = mA
ID = mA
VSD = 5 – IDRD = 0.98 V
VSD = 5 – IDRD = 2.26 V
VSD sat = VSG + VTP = 2.5 – 1.1 = 1.4V
2.26V > 1.4V
Bigger than VSD sat : saturation
0.98V < 1.4V
Smaller than VSD sat : non saturation
Answer: ID = mA and VSD = 0.98V
Power dissipation = ID x VSD = mW

14. LOAD LINE, ID versus VDS
Common source configuration i.e source is grounded.
It is the linear equation of ID versus VDS
Use KVL
VDS = VDD – IDRD
ID = -VDS + VDD RD RD

15. ID (mA)
VDS (V)
VGS
VDS ID
Q-POINTS
y-intercept
x-intercept

16. DC Analysis where source is NOT GROUNDED
For the NMOS transistor in the circuit below, the parameters are VTN = 1V and Kn = 0.5 mA/V2.

17. Calculate the value of VGS KVL at GS loop:R D = 2 k S G
24 k
+ 5 V
1 V I
5 V
Assume the transistor is biased in the saturation region, the drain current:
Calculate the value of VGS
KVL at GS loop:
0 + VGS+ 1(ID) = 0
VGS = 4 - ID
1 k
ID = mA
VGS= V
Replace in VGS equation in step 1
VGS = 4 - ID
ID = mA
VGS = V
Why choose VGS = V ?
Because it is bigger than VTN

18. Calculate VDSsat = VGS – VTN = 2.646 – 1 = 1.646 VR D = 2 k S G
24 k
+ 5 V
1 V I
5 V
Use KVL at DS loop
Calculate VDSsat = VGS – VTN = – 1 = V
Confirm your assumption: VDS > VDS sat , our assumption is correct
IDRD + VDS + IDRS – 5 – 5 = 0
1.354 (2) + VDS – 10 = 0
VDS = 10 – – = V
1 k

19. EXERCISE 1
The transistor parameters are VTN = 0.4 V, Kn = 3 mA/V2. The value of the current, ID = 0.35 mA
Calculate value of VDS and VGS
Calculate VDSsat . Is the transistor in saturation? ID
Answers:
Part (i)
VDS = 1.1 V
VGS = V
Part (ii)
VDS sat = V
YES

20. Answers: R1 = 422 kΩ R2 = 248 kΩ RD = 2.84 kΩ
EXERCISE 2
Assume that the transistor parameters are VTN = 0.8 V and Kn = 0.80 mA/V2. Given VDD = 5V and R1+ R2 = 670 kΩ, design the circuit such that ID = 0.88 mA and VDS = 2.5 V. Confirm any assumptions you make during your analysis.
Answers:
R1 = 422 kΩ
R2 = 248 kΩ
RD = 2.84 kΩ