1. ENEE 303 2nd Discussion

2. Discussion webpage

3. Contents
Pspice demonstration
MOSFET review

4. CMOS 4007(CA3600) Use Anl_misc.olb library: Add Library
ENEE 303 Fall 2017

5. CMOS 4007(CA3600) 2. Place part -> ANL_MISC -> CA3600E
ENEE 303 Fall 2017

6. CMOS 4007 Schematic 3. Connect the pins correctly.
~= 17mV calculation by hand, neglect channel modulation effect (lambda)
ENEE 303 Fall 2017

7. CMOS 4007 Simulation 4. Do the simulation
~= 17mV calculation by hand, neglect channel modulation effect (lambda)
ENEE 303 Fall 2017

8. CMOS 0.5u model
Add library: Path to Spice bicmos12.lib in VCL: C:\Cadence\SPB_16.6\tools\capture\library\pspice\bicmos12.lib
~= 17mV calculation by hand, neglect channel modulation effect (lambda)
ENEE 303 Fall 2017

9. CMOS 0.5u model
2. Edit configuration file under edit simulation profile
Add to Design
~= 17mV calculation by hand, neglect channel modulation effect (lambda)
ENEE 303 Fall 2017

10. CMOS 0.5u model 3. Edit the property of PMOS to change the value of W
4. Do the DC sweep on width
~= 17mV calculation by hand, neglect channel modulation effect (lambda)
ENEE 303 Fall 2017

11. Bipolar Junction Transistors
MOSFET
Bipolar Junction Transistors
ENEE 303 Fall 2016

12. Circuit Symbols of NOMS and PMOS
ENEE 303 Fall 2017

13. saturation occurs once vDS > vOV

14. The iD-vDS Characteristics for an NMOS Transistor
equation (5.14)
as vGS increases, so do the (1) saturation current and (2) beginning of the saturation region
ENEE 303 Fall 2017

15. Finite Output Resistance in Saturation
Q: What is l?
A: A device parameter with the units of V -1, the value of which depends on manufacturer’s design and manufacturing process.
much larger for newer tech’s
The adjacent figure demonstrates the effect of channel length modulation on vDS-iD curves
In short, we can draw a straight line between VA and saturation.
Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.
ENEE 303 Fall 2017

16. Regions of Operation of the NMOS Transistor
Cut-off region (no channel is formed):
Triode region:
Saturation (pinched-off channel) region:
ENEE 303 Fall 2017

17. Regions of Operation of the PMOS Transistor
Cut-off region (no channel is formed):
Triode region:
Saturation (pinched-off channel) region:
ENEE 303 Fall 2017

18. Example 1: NMOS
Given: Vtn = 0.5 V , mnCox = 0.4 mA/V2 , W/L = 0.72 mm / 0.18 mm = 4.0
Find: R that yields VD = 0.8 V
MOSFET in saturation
ENEE 303 Fall 2017

19. Example 2: NMOS Given: Vtn = 1 V , (mnCox)(W/L) = 1 mA/V2.
Neglect channel length modulation.
Find: All node voltages and branch currents.
ENEE 303 Fall 2017

20. Example 2: NMOS If ID = 0.89 mA, Transistor is indeed in saturation
Transistor is cutoff
Assume saturation,
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21. Example 3: PMOS
Problem Statement: Design the circuit so that transistor operates in saturation with ID = 0.5mA and VD = +3V. Let the PMOS transistor have Vtp = -1V and k’p(W/L) = 1mA/V2. Assume l = 0.
ENEE 303 Fall 2016

22. Example 4: CMOS
Problem Statement: The NMOS and PMOS transistors in the circuit are matched, with k’n(Wn/Ln) = k’p(Wp/Lp) = 1mA/V2 and Vtn = -Vtp = 1V. Assuming l = 0 for both devices.
Q: Find the drain currents iDN and iDP, as well as voltage vO for vI = 0V, +2.5V, and -2.5V.
1. Idp = idn = 1.125mA, vo = 0; 2.
ENEE 303 Fall 2017