Access the Instruction from Memory

Slides:

Advertisements

Similar presentations

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Computer Organization Lecture 13 - A Verilog.

Advertisements

Pipeline Example: cycle 1 lw R10,9(R1) sub R11,R2, R3 and R12,R4, R5 or R13,R6, R7.

EECE476 Lecture 7: Single-Cycle CPU Instruction Processing & Control Chapter 5, Sections 5.3, 5.4 The University of British ColumbiaEECE 476© 2005 Guy.

The Processor: Datapath & Control

Processor II CPSC 321 Andreas Klappenecker. Midterm 1 Tuesday, October 5 Thursday, October 7 Advantage: less material Disadvantage: less preparation time.

CMPUT Computer Organization and Architecture II1 CMPUT229 - Fall 2003 TopicE: Building a Data Path and a Control Path for a Microprocessor José Nelson.

ENEE350 Ankur Srivastava University of Maryland, College Park Based on Slides from Mary Jane Irwin ( )

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicH: Building a Data Path and a Control Path for a Microprocessor José Nelson.

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures1 Machine instructions execution steps (1) FETCH = Read the instruction.

The Datapath Andreas Klappenecker CPSC321 Computer Architecture.

The Processor: Datapath & Control. Implementing Instructions Simplified instruction set memory-reference instructions: lw, sw arithmetic-logical instructions:

Chapter 4 Sections 4.1 – 4.4 Appendix D.1 and D.2 Dr. Iyad F. Jafar Basic MIPS Architecture: Single-Cycle Datapath and Control.

COSC 3430 L08 Basic MIPS Architecture.1 COSC 3430 Computer Architecture Lecture 08 Processors Single cycle Datapath PH 3: Sections

Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]

1 A single-cycle MIPS processor  An instruction set architecture is an interface that defines the hardware operations which are available to software.

MIPS processor continued. In Class Exercise Question Show the datapath of a processor that supports only R-type and jr reg instructions.

Chapter 4 From: Dr. Iyad F. Jafar Basic MIPS Architecture: Single-Cycle Datapath and Control.

PC Instruction Memory Address Instr. [31-0] 4 Fig 4.6 p 309 Instruction Fetch.

MIPS processor continued

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

COM181 Computer Hardware Lecture 6: The MIPs CPU.

Computer Architecture Lecture 6.  Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions:

Design a MIPS Processor (II)

ECE/CS 552: Single Cycle Control Path

Single-cycle CPU Control

EE204 Computer Architecture

Single Cycle CPU - Control

Single Cycle CPU.

CS 230: Computer Organization and Assembly Language

Single-Cycle Datapath and Control

Computer Architecture

Multi-Cycle CPU.

Single Cycle Processor

Multi-Cycle CPU.

CS/COE0447 Computer Organization & Assembly Language

Discussion Session Week 10

MIPS processor continued

Designing MIPS Processor (Single-Cycle) Presentation G

CS/COE0447 Computer Organization & Assembly Language

Single-Cycle CPU DataPath.

CS/COE0447 Computer Organization & Assembly Language

CSCI206 - Computer Organization & Programming

Datapath & Control MIPS

Rocky K. C. Chang 6 November 2017

CSE378 Midterm Review Moore’s Law -- What are the two versions?

Composing the Elements

Composing the Elements

The Processor Lecture 3.3: Single-cycle Implementation

The Processor Lecture 3.2: Building a Datapath with Control

COMS 361 Computer Organization

COSC 2021: Computer Organization Instructor: Dr. Amir Asif

Lecture 14: Single Cycle MIPS Processor

Control Unit (single cycle implementation)

Access the Instruction from Memory

Computer Architecture Processor: Datapath

Review Fig 4.15 page 320 / Fig page 322

Data Path Diagrams.

MIPS processor continued

Instructors: Randy H. Katz David A. Patterson

CS/COE0447 Computer Organization & Assembly Language

Control Unit (single cycle implementation)

The Processor: Datapath & Control.

COMS 361 Computer Organization

MIPS Processor.

Processor: Datapath and Control

ELEC / Computer Architecture and Design Spring 2015 Pipeline Control and Performance (Chapter 6) Vishwani D. Agrawal James J. Danaher.

CS/COE0447 Computer Organization & Assembly Language

Presentation transcript:

Access the Instruction from Memory PC Address Next PC Logic Instruction Memory Simplified Overview Instruction Access the Instruction from Memory

Access the Data from Registers PC Address Next PC Logic Instruction Memory Simplified Overview Instruction Register File Access the Data from Registers

Perform the Instruction PC Address Next PC Logic Instruction Memory Simplified Overview Instruction Register File ALU Perform the Instruction

Write the Result PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Addr Register File Data Memory ALU Data Out Data In Write the Result

PC Next PC Logic Address Instruction Memory Simplified Overview Register File Data Memory ALU Data Out Data In Timing Assumption

MIPS - Lite Consider the following instructions for implementation INSTRUCTION OP FUNCT R type op rs, rt, rd add 0 32 subtract 0 34 AND 0 36 OR 0 37 set on less than 0 42 load word 35 na lw rt, imm(rs) store word 43 na sw rt, imm(rs) branch equal 4 na beq rs, rt,imm

Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT R1 R2 Rw Registers R1 R2 Rw Dw Dr1 Dr2

Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs R1 rt R2 rd Rw Registers R1 R2 Rw Dw Dr1 Dr2

Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs R1 rt x R2 rd rt Rw Registers R1 R2 Rw Dw Dr1 Dr2

Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs R1 rt x rt R2 rd rt x Rw Registers R1 R2 Rw Dw Dr1 Dr2

Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw Registers R1 R2 Rw Dw Dr1 Dr2

RegDst = Register Destination for the Write Register Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw Registers rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register

RegDst = Register Destination for the Write Register Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register

RegWrite = Write the selected register with Write Data Input Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register

1 1 0 0 RegWrite = Write the selected register with Write Data Input Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst 1 1 0 0 RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register

PC Next PC Logic Address Instruction Memory Simplified Overview Register File Data Memory ALU Data Out Data In

ALU Operation Control Lines ALU Control Code Function Bnegate Operation 0 00 and 0 01 or 0 10 add 1 10 subtract 1 11 set on less than

ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 subtract 0 34 AND 0 36 OR 0 37 set on less than 0 42 load word 35 na store word 43 na branch equal 4 na

ALUOp = 10 if the operation depends on the funct field 00 if add ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 10 subtract 0 34 10 AND 0 36 10 OR 0 37 10 set on less than 0 42 10 load word 35 na 00 store word 43 na 00 branch equal 4 na 01 ALUOp = 10 if the operation depends on the funct field 00 if add 01 if subtract

ALUOp = 10 if the operation depends on the funct field 00 if add ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 10 add subtract 0 34 10 subtract AND 0 36 10 and OR 0 37 10 or set on less than 0 42 10 slt load word 35 na 00 add store word 43 na 00 add branch equal 4 na 01 subtract ALUOp = 10 if the operation depends on the funct field 00 if add 01 if subtract

ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 10 add 010 subtract 0 34 10 subtract 110 AND 0 36 10 and 000 OR 0 37 10 or 001 set on less than 0 42 10 slt 111 load word 35 na 00 add 010 store word 43 na 00 add 010 branch equal 4 na 01 subtract 110

ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input a b Zero a b ALU Result ALU control funct ALUOp

ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 Dr2 a b Zero a b ALU Result ALU control funct ALUOp

Load Word & Store Word ( I – type ) lw rt, imm16 (rs) or sw rt, imm16 ( rs) op rs rt imm16 lw # load word M[ R[rs] + sign_ext(imm16) ] R[rt] sw # store word R[rt] M[ R[rs] + sign_ext(imm16) ]

ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) a b Zero a b ALU Result ALU control funct ALUOp

ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b Zero a b ALU Result ALU control funct ALUOp

ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b Zero Dr1 a b ALU Result Dr2 1 sign ext imm 6 ALU control ALUSrc funct ALUOp

ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b ALUSrc = ALU second reg control Dr1 a b Zero ALU Result Dr2 1 sign ext imm 6 ALU control ALUSrc funct ALUOp

ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b 0 1 1 0 ALUSrc = ALU second reg control Dr1 a b Zero ALU Result Dr2 1 sign ext imm 6 ALU control ALUSrc funct ALUOp

PC Next PC Logic Address Instruction Memory Simplified Overview Register File Data Memory ALU Data Out Data In

Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm MemWrite Result Addr Dr Dr2 Dw MemRead Data Memory

1 1 0 0 RegWrite = Write the selected register with Write Data Input Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst 1 1 0 0 RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register

Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemWrite Result Addr Dr Dw Dr2 Data Memory MemRead

Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control 0 0 1 0 MemWrite MemRead MemWrite Result Addr Dr Dw Dr2 Data Memory MemRead

Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control 0 0 1 0 MemWrite MemRead 0 1 0 0 MemWrite Result Addr Dr Dw Dr2 Data Memory MemRead

Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control 0 0 1 0 MemWrite MemRead MemtoReg 0 1 0 0 mux MemWrite 1 to Register File Dw Result Addr Dr Dw Dr2 MemtoReg Selects data memory or ALU output to Register Write Data Data Memory MemRead

Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control 0 0 1 0 MemWrite MemRead MemtoReg 0 1 0 0 0 1 x x mux MemWrite 1 to Register File Dw Result Addr Dr Dw Dr2 MemtoReg Selects data memory or ALU output to Register Write Data Data Memory MemRead

PC Next PC Logic Address Instruction Memory Simplified Overview Register File Data Memory ALU Data Out Data In

add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 ? imm16 sign ext 16 32

add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 16 32 Branch

add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic add lw sw beq Control Branch 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 16 32 Branch

add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic add lw sw beq Control 0 0 0 1 Branch 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 16 32 Branch

Control Summary Inputs R type lw sw beq Op 000000 100011 101011 000100 Outputs RegDst 1 0 x x ALUSrc 0 1 1 0 MemtoReg 0 1 x x RegWrite 1 1 0 0 MemRead 0 1 0 0 MemWrite 0 0 1 0 Branch 0 0 0 1 ALUOp1 1 0 0 0 ALUOp2 0 0 0 1

Review Fig 4.15 page 320 / Fig. 4.17 page 322 Review Timing

Add Jump Instruction j Label go to Label op address 2 address 6 bits 26 bits The complete 32 bit address is : address 00 4 bits 26 bits 2 bits Upper 4 bits of the Program Counter, PC jump uses word addresses address * 4 = address:00 This is Pseudodirect Addressing. Note: 256 MB word boundaries

Jump Instruction Data Path 28 32 shift left 2 address Instruction[25-0] : 1 PC+4 (31-28) 4 4 “Other” Next Instr Logic Add PC

Jump Instruction Data Path Jump = Opcode(2) Jump 28 32 shift left 2 address Instruction[25-0] : 1 PC+4 (31-28) 4 4 “Other” Next Instr Logic Add PC