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Single Cycle CPU.

Published byLoreen Beasley Modified over 6 years ago

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Presentation on theme: "Single Cycle CPU."— Presentation transcript:

1 Single Cycle CPU

2 Operations Implemented
R-type add sub and or Load/Store ldur stur Conditional branch cbz Unconditional branch b

3 Register File Read Select D E C O R Data Out Write Select Data Out
M U X D E C O R Data Out Write Select M U X Data Out Write Enable Clock Data In Register File

4 R-Type Instruction Path
Rn Write ALU Rm Select Registers Rd R-Type Instruction Path

5 Load/Store Instruction Path
Rn ALU Registers Select Rt address Data Memory 1 M U X data out Sign Ext data in DT Addr Load/Store Instruction Path

6 Conditional Branch Instruction Path
PC + 4 ADD Shift Left 2 ALU Registers zero (to select condition) Select Rt Sign Ext Cond Br Addr Conditional Branch Instruction Path

7 Immediate Instruction Path (not implemented)
Rn Write ALU Registers Select Rd Zero Ext Immediate Immediate Instruction Path (not implemented)

8 Instruction Path with Instruction from Memory
PC + 4 ADD branch addr Shift Left 2 5-9 Write Zero ALU PC Instruction Memory 16-20 M U X Registers 0-4 address 1 M U X Data Memory 1 data out M U X 0-31 Sign Ext data in Instruction Path with Instruction from Memory (R-type, Load/Store, Conditional branch, no immediate)

9 Incrementing the Program Counter and computing branch address
4 ADD PC + 4 ADD branch addr Shift Left 2 5-9 Zero ALU PC Instruction Memory 16-20 M U X Registers 0-4 address 1 M U X Data Memory 1 data out M U X 0-31 Sign Ext data in

10 4 Zero ADD ADD ALU PC Instruction Memory Registers Data Memory M U X
1 M U X 4 ADD ADD Shift Left 2 5-9 ALU PC Instruction Memory 16-20 Zero M U X Registers 0-4 address 1 M U X Data Memory 1 M U X data out data in 0-31 Sign Ext

11 4 Zero ADD ADD ALU PC Instruction Memory Registers Data Memory M U X
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out Sign Ext data in 0-31 ALU CTRL 21-31

12 Control Lines, Top to Bottom
A Conditional Branch (CBZ) B MemToReg C MemRead D MemWrite E ALUSrc F ALUOp G RegWrite H Reg2Loc

13 Start to 2 ns 4 Zero ADD ADD ALU PC Instruction Memory Registers Data
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out Sign Ext data in 0-31 Start to 2 ns ALU CTRL 21-31

14 R-Type Register Rd 2 - 3 ns 4 Zero ADD ADD ALU PC Instruction Memory
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out R-Type Register Rd 2 - 3 ns Sign Ext data in 0-31 ALU CTRL 21-31

15 R-Type ALU 3 - 5 ns 4 Zero ADD ADD PC Instruction Memory Registers ALU
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write PC Instruction Memory 16-20 Zero M U X Registers ALU write read 0-4 1 address M U X Data Memory 1 M U X data out R-Type ALU 3 - 5 ns Sign Ext data in 0-31 ALU CTRL 21-31

16 R-Type Reg Write 5 - 6 ns 4 Zero ADD ADD PC Instruction Memory
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write PC Instruction Memory 16-20 Zero M U X Registers ALU write read 0-4 1 address M U X Data Memory 1 M U X data out R-Type Reg Write 5 - 6 ns Sign Ext data in 0-31 ALU CTRL 21-31

17 Load D-Word 0 - 2 ns 4 Zero ADD ADD ALU PC Instruction Memory
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out Load D-Word 0 - 2 ns Sign Ext data in 0-31 ALU CTRL 21-31

18 Load D-Word Reg Read 2 - 3 ns 4 Zero ADD ADD ALU PC Instruction Memory
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out Load D-Word Reg Read 2 - 3 ns Sign Ext data in 0-31 21-31 ALU CTRL

19 Load Word Address Comp 3 - 5 ns 4 Zero ADD ADD PC Instruction Memory
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write PC Instruction Memory 16-20 Zero M U X Registers ALU write read 0-4 1 address M U X Data Memory 1 M U X data out Load Word Address Comp 3 - 5 ns Sign Ext data in 0-31 21-31 ALU CTRL

20 Load D-Word Memory Access 5 - 7 ns 4 Zero ADD ADD PC Instruction
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write PC Instruction Memory 16-20 Zero M U X Registers ALU write read 0-4 1 address M U X Data Memory 1 M U X data out Load D-Word Memory Access 5 - 7 ns Sign Ext data in 0-31 21-31 ALU CTRL

21 Load D-Word Write Back 7 - 8 ns 4 Zero ADD ADD PC Instruction Memory
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write PC Instruction Memory 16-20 Zero M U X Registers ALU write read 0-4 1 address M U X Data Memory 1 M U X data out Load D-Word Write Back 7 - 8 ns Sign Ext data in 0-31 21-31 ALU CTRL

22 CBZ 0 - 2 ns 4 Zero ADD ADD ALU PC Instruction Memory Registers Data
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out CBZ 0 - 2 ns Sign Ext data in 0-31 ALU CTRL 21-31

23 CBZ Register Rd 2 - 3 ns 4 Zero ADD ADD ALU PC Instruction Memory
1 M U X ADD 4 ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out CBZ Register Rd 2 - 3 ns Sign Ext data in 0-31 21-31 ALU CTRL

24 CBZ taken ALU test 3 - 5 ns 4 Zero ADD ADD PC Instruction Memory
1 M U X 4 ADD ADD Shift Left 2 C O N T R L A B C D E F G H 21-31 5-9 write PC Instruction Memory 16-20 Zero M U X Registers ALU write read 0-4 1 address M U X Data Memory 1 M U X data out CBZ taken ALU test 3 - 5 ns Sign Ext data in 0-31 21-31 ALU CTRL

25 Unconditional branch added (AA)
1 M U X ADD 4 ADD Unconditional branch added (AA) Shift Left 2 C O N T R L AA A B C D E F G H 21-31 5-9 write ALU PC Instruction Memory 16-20 Zero M U X Registers write read 0-4 1 address M U X Data Memory 1 M U X data out Sign Ext data in 0-31 Additional logic In Sign Ext ALU CTRL 21-31

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