Performed by: Erez Davidi / Aviad Zrihen Instructor: Yaniv Ben-Yitzhak המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Request – Response patterns predictor for CMP Semester: Spring 2013

Overview המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory  NoC: Network-on-Chip (NoC) is a new approach to design the communication subsystem of System-on- a-Chip (SoC) and Chip-Multi-Processors (CMP). As chip multiprocessors (CMPs) become the most effective way to scale up and improve microprocessor performance, the design of on-chip networks is becoming critically important.  Reducing latencies: The CMP transaction latencies can be reduced by using a request-response pattern predictor which setup a speculative pipeline – and thus reduce the number of required stages.  Principles of work: Each router that is connected to the module, has a request-response predictor of that kind. For each request that passes through the router, the predictor predicts the expected arrival time of the response from the destination to the predictor’s router. That way, the router (using the information from the predictor) can obtain an open channel for the data transfer to the source router, to allow the “pipeline” to be prepared properly for the data arrival, and that way to significantly minimize the transfer time.

System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory The goal of this project was to design and implement a request-response predictor for NoC-based CMP. The predictor will receive as input different transactions that are passing through the NoC system between the cores, which are classified as “Request messages” or “Response messages”. These inputs will be inserted into the predictor’s system using a test bench file that we created, which is based on a trace file we received from a parallel project. The predictor’s output for each request message in the system will be an estimated time for the same message’s response to arrive, based on similar past messages – thus creating a learning machine. The estimated delay time between the request and the response messages will be used by the system’s routers which will “get prepared” for the response (in terms of time period), resulting in latencies reduction along the path of the response message by obtaining an “open channel” for it in the pipeline.

System Architecture - Predictor המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Detailed Architecture - Units המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Average calculation unitStatistic unit Algorithm unit

Detailed flow המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Request message Response message Message type Classification: