1. Performed by:Yulia Turovski Lior Bar Lev Instructor: Mony Orbach המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Mid-Semester Presentation I Subject: High-Speed Communication Channel(s) Switch Winter semester 2010 1

2. Outline המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Reminder – Motivation and Goal Switch structure Switching algorithm (“Router”) SerialLite II component Packet size consideration Implemented protocol Validation method Gantt diagram

3. Motivation and Goal המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Motivation: High-speed communication between devices. Utilizing high frequency achievable with new hardware. Demand for reliable communication Goal: Design & implementation of high speed communication switch. Use of advanced communication protocols. Connect between as many devices as possible. Best transmission rate possible.

4. Priority vs. Data המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 SerialLite II can use two types of ports: Priority ports Sends packets with higher priority Includes internal DLL functions (protocol described later) Can stop data packet in middle of transmission Will be routed by fullest queue first Data ports Sends “regular” packets Example: video streaming Doesn’t include internal DLL functions We can implement one later Will be routed by time priority using multiple-out queues Address 8bitTimestamp 16 bitData 29Byte Address 8bitData 31Byte Data Priority

5. Priority Path Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 SerialLite II in out in out inout in out Router Routing Tables (RAM) config FIFO

6. Data Path Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 SerialLite II in out in out inout in out Router Routing Tables (RAM) config Time priority queue

7. Buffer Design המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Entrance buffers offer 4 highest-priority packets each Priority port presents oldest message available for each output port Chosen for each port is the packet from the most occupied input queue Data port presents the packet with earliest stamp for each output port Chosen is the earliest-stamped packet for each output port Each port can contribute 0-3 packets each cycle depending on availability and priority of packets. Getting messages from inside the queue requires additional logic Buffer-private stamping for fifo packets and priority logic 4

8. Switching Algorithm המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Translate addresses using translation tables Hold start index For each output port j For each priority in port I (start index to N and then 1 to start-1) Each buffer offers first message for each output port (4) If size(i)>Max Max=size(i), Pchoose(j)=i Transfer Pchoose[j] For each data in port I (start index to N and then 1 to start-1) Each buffer offers oldest message for each output port (4) If out(j).time<oldest(j) Oldest(j)=i, Dchoose(j)= i Transfer Dchoose[j] Eventually we can implement each algorithm for any port 4

9. SerialLite II Megafunction המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 DLL and PHY Multiple lanes One lane per connection Constant packet size Small or large? CRC checks included (16/32) We use 16 Physical layer enhancements Buffers for quality of service Holds up to 8 packets. If full – no packets inserted Optional use of flow control logic (costs space)

10. SerialLite II Limitations המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Highest rate possible with stratix II GX – 6.75 Gbps On other devices highest rate may be as low as 3.125 Gbps Space resources for 4 SerialLite II ports with both priority and data packets (worst case scenario): 1 Priority port: 1675 ALUTs + 1284 logic registers, 12 M512s and 22 M4K 1 Data port: 1381 ALUTs + 1075 logic registers, 12 M512s and 12 M4K Total, assuming ALUT=LREG=LE: 21660 LEs, 96 M512s and 136 M4Ks Available: 90,960 LEs, 488 M512 and 408 M4Ks Cores consume 24% of logic space and average of 25% of memory – reasonable for it’s advantages.

11. Packet size consideration המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Transfer rate – 6Gb/sec = 0.75GB/sec Assuming clock frequency – 200 MHz Transfer rate = clock frequency*packet size Rate met for packets >= 3.75B 16 byte packet allows blocking switching!

12. Protocol המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 7 Priority packets Every packet is a priority packet (no regulars) Retry on error Similar to selective repeat (NACK) Characteristics of GBN (timeout, out of order) Recovery. Data packets have no built in DLL protocol

13. Validation Method המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 8 Module with 4 SerialLite II instances Random / Pre-prepared addressed packets (scenario) Arranges two buffers for each port After completion of transfer – comparing packets Errors in switching Errors in data Order of reception vs. generation (stepper) OFFLINE In simulation – using test-bench Possibility of adding test indicators (i.e. buffer full) After synthesis – using another device

14. Validation Method (2) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Port I Port II Port III Port IV Port I Port II Port III Port IV Config out gold res gold res gold res gold res inX4 Test deviceSwitch

15. Project Schedule המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 9 Tasks 27/12-2/13-9/110-16/117-23/124-30/131/1-6/27-13/214-20/221-27/2 Mid presentation Router coding+sim In/out buffer coding+sim SerialLite II variation End- semester presentation Minimum goal: showing each block and its simulation waves. Maximum goal: showing entire switch simulation with limited scenario test bench.