ILC/EUDET developments at LAL Scientific council 23/9/05 B. Bouquet, J. Fleury, C. de La Taille, G. Martin-Chassard LAL Orsay

23 sep 2005C. de La Taille ILC developments LAL scientific council 2 Integrated Detector Design Tracking system EM Cal HAD Cal Muon system/ tail catcher VXD tag b,c jets Calorimetry : Jet resolution Particle flow algorithm Compactness Analog/digital © A. White

23 sep 2005C. de La Taille ILC developments LAL scientific council 3 Calorimetry at ILC : challenges for electronics CALICE = W-Si Calorimeter Precision measurements : ~10%/√E good linearity (‰ level) Good inter-calibration (% level) Low crosstalk (‰ level) Large dynamic range (15 bits) 0.1 MIP -> MIPS Auto-trigger on MIP Low noise << MIP = 40, 000 e- Hermeticity : no room for electronics ! High level of integration : « SoC » Ultra-low power : ( << mW/ch ) 30 Mchannels « Tracker electronics with calorimetric performance » ATLAS LAr FEB 128ch 400*500mm 1 W/ch FLC_PHY3 18ch 10*10mm 5mW/ch Ultra-low POWER is the KEY issue

23 sep 2005C. de La Taille ILC developments LAL scientific council 4 CALICE ECAL Front-End ASIC Power Cycling Auto-trigger on ½ MIP Internal ADC Readout integration is the key element of compact detector Keep small Moliere radius for good shower separation

23 sep 2005C. de La Taille ILC developments LAL scientific council 5 CALICE : two axes of R&D Physics prototype demonstrate physics performance validate simulation tools FLC_PHY ASICs Running at DESY since jan 05 Technological prototype demonstrate detector feasibility FLC_TECH ASICs Starting just now… ≈ 5000 (4200) 1700 (1500) ECAL Module ECAL 1700 (1500) 1000 (840) 210 (170) HCAL

23 sep 2005C. de La Taille ILC developments LAL scientific council 6 FLC_PHY3 : W-Si front-end electronics FLC_PHY3 in a nutshell MIP/noise = 9, Emax = 1000 MIPS 5 mW/channel 2000 chips prod. in 2004 (0.8µm BiCMOS) 6x6 1 cm 2 photodiode wafers FLC_PHY3 18ch readout ASIC Calibration ASIC

23 sep 2005C. de La Taille ILC developments LAL scientific council 7 FLC_SiPM : readout ASIC for AHCAL SiPMs Analog Hadronic calorimeter physics prototype (DESY) : tiles + fibers “Silicium PM” photodetector Readout ASIC derived from FLCPHY3 + several new features (DAC, bi-mode…) first ASIC to readout SiPM 1000 chips delivered in less than 1yr © F. Sevkov DESY Amplifier Board FLC_SiPM 18ch readout ASIC (LAL)

23 sep 2005C. de La Taille ILC developments LAL scientific council 8 Towards module 0 : technological prototype Front-end ASICs embedded in detector Very high level of integration Ultra-low power with pulsed mode All communications via edge 4,000 ch/slab, minimal room, access, power Keep hermeticity Data out (~Mbyte/s/slab) optical, wireless ? Development in the framework of EUDET ≈ 5000 (4200) 1700 (1500) ECAL Module ECAL 1700 (1500) 1000 (840) 210 (170) HCAL MAX 1700 (1500) Détecteur SLAB

23 sep 2005C. de La Taille ILC developments LAL scientific council 9 ECAL – détecteur SLAB Minimize thickness for best Moliere radius PCB: 2100 µm shielding: 100 µm glue: 110 µm wafer: 525 µm ground foil: 30 µm gap: 445 µm 3300 µm shielding: 100 µm cables: 400 µm PCB: 600 µm glue: 100 µm wafer: 500 µm ground foil: 50 µm chip: 800 µm Design Proto. Physique 1750 µm New Design SLAB

23 sep 2005C. de La Taille ILC developments LAL scientific council 10 ASIC developments at LAL in FLC_TECH1 : moving into SiGe 0.35µ 4ch preamp + shaper + power cycling (Apr 04) 30 µW in pulsed mode ENC = 1000 Cd=27pF (measured) First demonstration of power cycling FLC_PHY4 : integrating the ADC FLC_PHY3 architecture basis Complete Power pulsing No external components Integrated 12bit ADC (IP AMS, collab LPNHE) Submitted july 05 ADCs Several ADC architectures being studied FLC shaping Detector capacitance Autotrigger

23 sep 2005C. de La Taille ILC developments LAL scientific council 11 EUDET PROPOSAL (JRA3 calorimetry) Electromagnetic calorimeter (LLR,LAL) Prototype of a (1/3) module cm long, 12 cm wide 30 layers (Analog) Hadronic calorimeter (DESY,IPASCR) Digital Hadronic calorimeter ( VFCAL (INPPAS, AGH-UST,TAU ) DAQ (UCL) Front-End electronics (DESY, LAL, LPC) Complete readout ASIC with power cycling and integrated ADC ASIC for SiPMs and digital HAdronic calorimeter 1.5m Technologic prototype

23 sep 2005C. de La Taille ILC developments LAL scientific council 12 EUDET milestones : em calo Preliminary : to be clarified Detector optimization (LLR+LAL) Cell size ? Number of layers ? More input from physicists needed Si sensors (LLR) How to achieve the target price ? Needed to develop FE ASIC (capacitance, # of channels, max signal…) Front-end ASIC (LAL+LPC+?) Close to final architecture needed. Choices need to be validated 2 prototypes foreseen in july 06 and 07 Small production of 3000 chips in 2008 Front-End boards (LAL+LLR) Thickness tightly controlled, no height for components, must be “sticthable” 2 prototypes foreseen jan 06 and jan 07 System level studies Data acquisition (UCL+LLR)

23 sep 2005C. de La Taille ILC developments LAL scientific council 13 LAL in EUDET Manpower committed : 192 ppm M.Bouchel (24ppm) B.Bouquet (48ppm) T.Caceres (24ppm) J Fleury (48ppm) CdLT (24ppm) G.Martin-Chassard (24ppm) Money allocated by EU: 330 k€ 135 k€ for postdoc 100 k€ for ASIC developments Request for LAL Request for in2p3

23 sep 2005C. de La Taille ILC developments LAL scientific council 14 conclusion Responsibility for Front-end ASIC(s) Analog design half-way through More work needed on ADCs Digital part to start soon (data formatting, daisy chaining) HCAL front-end can be advanced in parallel Still a lot of work to validate design Commitments for EUDET 16 person.yr (4 years) Build a (part) of technological prototype Will receive 1 postdoc for measurements 100k€ for prototype developments + preseries Additional funding will be needed Many collaborations initiated Inside in2p3 for FE electronics With DESY, Korea…