1. C. de La Taille IN2P3/LAL Orsay
EUDET FRANCE
C. de La Taille
IN2P3/LAL Orsay

2. EUDET JRA3 milestones (except FCAL)
Jun 06 : Analog ASIC prototype 1 available
Sept 06 : PCI card available
Jun 07 : AHCAL Front-End board and modified stack ready
Jun 07 : DHCAL VFE conceptual design ready
Jul 07 : Analog ASIC prototype 2 available
Jun 08 : Integrated ASIC available
Jun 08 : final DAQ available
Jan 09 : DHCAL VFE engineering design ready
Jan 09 : Front end electronics infrastructure available
Mar 09 : AHCAL front end boards available
Jun 09 : integrated system available
Dec 09 : construction complete
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

3. CdLT CERN meeting on CALICE/EUDET electronics
EUDET planning
Sept 06 : DHCAL ASIC submitted
Nov 06 : ECAL ASIC submitted
Mar 07 : DHCAL front-end board designed
Mar 07 : ECAL PCB R&D
Jun 07 : AHCAL ASIC submission
Mar 08 : DHCAL, ECAL and AHCAL ASIC production
Jun 08 : ASIC tests
Jun 08 : ECAL PCB production
Sept 09 : mounting of ASICs and tests of ~40 PCBs
Mar 09 : mounting of wafers + cosmic tests
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

4. EUDET funding at CNRS (hardware)
Spendings : 335 k€
Tungsten sheet : 60 k€ (LLR)
Structure computing : 22 k€ (LLR)
Moulds : 70 k€ (LLR)
PCBs : 15 k€ (LLR)
Si wafers : 60 k€ (LLR)
AISC development (DHCAL) : 13 k€ (LAL+LLR)
ASIC protoptypes : 95 k€ (LAL + LPCC)
Has disappeared : ASIC + PCB production : 161 k€
Attributed : 185 k€
LLR : 77 k€ ECAL + 7 k€ VFE
LAL : 95 k€ VFE
LPC : 5 k€ VFE
Committed
LLR : 150 k€
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

5. CdLT CERN meeting on CALICE/EUDET electronics
EUDET consumables
CONSUMABLES
TOTAL
allocated 2006
spent dec06
allocated 1/2007
spent jul07
allocated 7/2007
CNRS/EP TOT
84,550 €
16,600 €
59,000 €
9,950 €
- €
29,000 €
CNRS/EP ECAL
76,950 €
9,000 €
CNRS/EP FEE
7,600 €
CNRS/LAL FEE
95,000 €
2,000 €
45,000 €
56,000 €
25,000 €
CNRS/LPC FEE
5,000 €
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

6. CdLT CERN meeting on CALICE/EUDET electronics
EUDET Staff
TEMP STAFF
TOT
allocated 2006
spent dec06
allocated 2007
spent apr07
CNRS/EP TOT
275,000 €
31,000 €
27,000 €
125,000 €
- €
CNRS/EP ECAL 30
12,500 €
20,000 €
50,000 €
CNRS/EP FEE 24
150,000 €
18,500 €
7,000 €
75,000 €
CNRS/LAL FEE 32
135,000 €
35,000 €
CNRS/LPC FEE
10,000 €
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

7. CdLT CERN meeting on CALICE/EUDET electronics
Money spent at LAL
2006 : 2 k€
2 k€ testboards
2007 : 50 k€
16k€ : HaRDROC prototype
4 k€ : testboards
5 k€ : 70 more chips
5 k€ : DHCAL PCB
20 k€ : SKIROC prototype
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

8. CdLT CERN meeting on CALICE/EUDET electronics
EUDET : ECAL module
Electromagnetic calorimeter
Prototype of a (~ 1/6) module 0 : one line & one column
150 cm long, 12 cm wide 30 layers
channels
Test full scale mechanics + PCB
Can go in test beam
Test full integration + edge communications
To be delivered in 2009
©M. Anduze (LLR)
Slab FE
FPGA
PHY
VFE
ASIC
Data
Clock+Config+Control
Conf/
Clock
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

9. EUDET - Detector slab (2)
“end” PCB
Connection between 2 PCB
7 “unit” PCB
Exploded view
Chip « inside »
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

10. AHCAL architecture To DAQ Module data concentrator 38 layers
80000 tiles
Typical layer
2m2
2000 tiles
Layer data
Concentrator
(control, clock
and read FEE)
FEE:
32 ASICs
(64-fold)
4 readout
lines / layer
EUDET: Mechanical structure,
electronics integration:
DESY and Hamburg U
Instrument one tower (e.m. shower size)
+ 1 layer (few 1000 tiles)
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

11. CdLT CERN meeting on CALICE/EUDET electronics
DHCAL architecture
First detector with 2nd generation ASCIs and 2nd generation DAQ
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

12. DAQ Structural Overview
ASICs
Front-End (FE)
FE-Interface (DIF): Detector specific
FE Link/Data Aggregator (LDA): Generic
Data-link (FE to Off-Detector Receiver)
Control-link (C+C to FE)
DAQ PC
Off-Detector Receiver (ODR)
Control data-link (Clock, Control to FE)
Data Store
ASICs
DIF FE
LDA
Control-link
Data-link
PC/s
ODR
Store
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

13. UK Read-out work (ECAL FE)
Slab
Detector Interface (Cam)
Spec + hardware
DIF to Link/Data Aggregator (Cam/Man)
Data aggregate, format (Man)
Hardware + firmware
LDA to ODR opto-link (Man, UCL)
ODR (RHUL, UCL, Cam)
firmware
ODR to disk (RHUL)
Driver software
Local Software DAQ (RHUL)
Full blown Software DAQ (RHUL, UCL, [IC])
DIF
LDA
Opto PC
ODR
Opto
Driver
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics