1. CALICE/EUDET Electronics in 2007
C. de La Taille
IN2P3/LAL Orsay

2. Tasks for CALICE/EUDET in 2007
Complete physics prototype
Add and test DHCAL, complete physics program
Test effect of em shower on ASIC
Measure performance of 2nd generation ASIC
On testbench in different labs
DHCAL ECAL, AHCAL
Test 2nd generation DAQ (UK)
Design Very Front-End boards with integrated ASICs
ECAL board with FLC_PHY4
DHCAL board with HARDROC
Design EUDET module(s) (demonstrator)
Identify responsibilities
Organize schedule
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

3. CdLT CERN meeting on CALICE/EUDET electronics
EUDET : ECAL module
Electromagnetic calorimeter
Prototype of a (~ 1/6) module 0 : one line & one column
150 cm long, 12 cm wide 30 layers
channels
Test full scale mechanics + PCB
Can go in test beam
Test full integration + edge communications
To be delivered in 2009
©M. Anduze (LLR)
Slab FE
FPGA
PHY
VFE
ASIC
Data
Clock+Config+Control
Conf/
Clock
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

4. EUDET - Detector slab (2)
“end” PCB
Connection between 2 PCB
7 “unit” PCB
Exploded view
Chip « inside »
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

5. AHCAL architecture To DAQ Module data concentrator 38 layers
80000 tiles
Typical layer
2m2
2000 tiles
Layer data
Concentrator
(control, clock
and read FEE)
FEE:
32 ASICs
(64-fold)
4 readout
lines / layer
EUDET: Mechanical structure,
electronics integration:
DESY and Hamburg U
Instrument one tower (e.m. shower size)
+ 1 layer (few 1000 tiles)
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

6. CdLT CERN meeting on CALICE/EUDET electronics
DHCAL architecture
First detector with 2nd generation ASCIs and 2nd generation DAQ
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

7. DAQ Structural Overview
ASICs
Front-End (FE)
FE-Interface (DIF): Detector specific
FE Link/Data Aggregator (LDA): Generic
Data-link (FE to Off-Detector Receiver)
Control-link (C+C to FE)
DAQ PC
Off-Detector Receiver (ODR)
Control data-link (Clock, Control to FE)
Data Store
ASICs
DIF FE
LDA
Control-link
Data-link
PC/s
ODR
Store
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

8. CdLT CERN meeting on CALICE/EUDET electronics
FE – More thoughts
Each DIF can connect directly to an LDA for stand-alone operation OR
Combine on single PCB, with single FPGA
Capabilities depend on PCB loading
Operate as stand-alone, or as master-slave (aggregator)
Firmware development 2 tiered
Eg: ECAL:
Slave-Out
FPGA
Local Control In
Detector
Opto
Detector
Fibre
Slab connector
Detector
Power In
Slaves-In
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

9. UK Read-out work (ECAL FE)
Slab
Detector Interface (Cam)
Spec + hardware
DIF to Link/Data Aggregator (Cam/Man)
Data aggregate, format (Man)
Hardware + firmware
LDA to ODR opto-link (Man, UCL)
ODR (RHUL, UCL, Cam)
firmware
ODR to disk (RHUL)
Driver software
Local Software DAQ (RHUL)
Full blown Software DAQ (RHUL, UCL, [IC])
DIF
LDA
Opto PC
ODR
Opto
Driver
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics

10. CdLT CERN meeting on CALICE/EUDET electronics
23 mar 2007
CdLT CERN meeting on CALICE/EUDET electronics