1. Prof. Joongho Choi CMOS SEQUENTIAL CIRCUIT DESIGN Integrated Circuits Spring 2001 Dept. of ECE University of Seoul

2. Prof. Joongho Choi Combinational vs. Sequential Logic Combinational Logic OUT(t)  IN(t) Sequential Logic OUT(t)  IN(t)  IN(t-kT)  OUT(t-kT) Positive Feedback Charge on Cap. Positive Feedback Charge on Cap.

3. Prof. Joongho Choi Sequential Logic w/ Positive Feedback Two Inverters in Positive Feedback STATIC

4. Prof. Joongho Choi Bi-stability Transition Region Stable Regions Slope (Gain) >1

5. Prof. Joongho Choi SR Latch NOR-Based S R Q S R Q S R QQ 0 1 0 1 0 0 1 1 Q 1 0 0 Q 0 1 0 S R Q Q Q S R Q S R Q Q 1 0 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1 Q Q NAND-Based

6. Prof. Joongho Choi JK Flip-Flop LL H H H ? HLHL L L  H L  L H H  H H Q Q  =H

7. Prof. Joongho Choi T-FF & D-FF

8. Prof. Joongho Choi Race Problem of Latch

9. Prof. Joongho Choi Master/Slave Flip-Flop masterslave H L H H L L H L One-Catching Level-Sensitive Input Data Valid @  =High One-Catching Level-Sensitive Input Data Valid @  =High

10. Prof. Joongho Choi Edge-Triggered Operation 1

11. Prof. Joongho Choi Edge-Triggered Operation 2

12. Prof. Joongho Choi Flip-Flop Timing Constraints Setup Time t setup Hold Time t hold Propagation Delay t pFF

13. Prof. Joongho Choi Flip-Flop Timing Example T > t pFF + t p,comb + t setup FF’s LOGIC t p,comb  QY

14. Prof. Joongho Choi CMOS Latches

15. Prof. Joongho Choi Pseudo-Static D-Latch  =High (Data I/O)  =Low (Data Store)

16. Prof. Joongho Choi M/S D-FF (pseudo-Static)  =High  New Data In & Previous Data Store  =Low  New Data Out & New Data Store

17. Prof. Joongho Choi M/S D-FF (pseudo-Static) Problem

18. Prof. Joongho Choi M/S D-FF Problem Solution Non-Overlapping 2-Phase Clocks

19. Prof. Joongho Choi Dynamic M/S D-FF