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Page 1 Sequential Logic Basic Binary Memory Elements.

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Presentation on theme: "Page 1 Sequential Logic Basic Binary Memory Elements."— Presentation transcript:

1 Page 1 Sequential Logic Basic Binary Memory Elements

2 Page 2 Chapter Overview  Sequential Networks  Simple Circuits with Feedback  R-S Latch  J-K Flipflop  Edge-Triggered Flipflops  Realizing Circuits with Flipflops  Choosing a FF Type  Characteristic Equations  Conversion Among Types

3 Page 3 Sequential Circuits Circuits with Feedback: Some outputs are also inputs Sequential logic forms basis for building "memory" into circuits These memory elements are primitive sequential circuits X1 X2. Xn Z1 Z2. Zm Combinational Logic Inputs Lights and timer control Storage(state) Combinational Logic clk Sequential logic Clk: Clock: Syncronizes the operations

4 Page 4 Sequential Circuits  Binary Storage element: A cell capable of ‘storing’ one bit of information as long as we want, even if we change the input  These units are called ‘bistable’  Synchronous: Can change only at discrete instants of time(managed by the clock)  Asyncronous: Can change anytime Output Clock State: 0 or 1 Input Clock

5 Page 5 Sequential Circuits  A Clock Signal:A sequence of ‘clock pulses’ with a fixed period Timing Diagram for a clock pulse: Changes in states and output occur only at these points for syncronous circuits

6 Page 6 Bi-stable Storage Element Characteristics  All bistable binary storage elements must have the following characteristics  The element must have two stable states  For a “stable” input configuration, the element can be in either of two possible states, set (1) or reset (0)  Inputs must exist to modify or hold FF state  A set of input and values must be able to change the stored value as well as hold the value  The present element state must be detectable  There must be an element output to determine what is the state of the element

7 Page 7 Bistable Binary Storage Elements  Simple Circuits with Feedback  Primitive memory elements are created from cascaded gates where output is fed back to input  Simplest gate component:buffer or inverter:has a delay time tpd  Inverter: Basis for commercial static RAM designs  Present the input, remove it and the buffer will keep it Tpd:prop.delay for the buffer The input is effectively stored for tpd units. İf output is connected to input, This value is kept indefinitely But no change is possible Replace inverters with nand or nor gates to obtain the ‘Basic Latch’

8 Page 8 Basic RS Latch Cross-Coupled NOR Gates: RS Latch (Nor Gate: The output is 0 if there is at least one 1 at the input, 1 when both inputs are zero) İf R=0, S=1 initially, Q=1, Q’=0 (set) Now make R=0, S=0 Q=1, Q’= 0 (/no change, hold) Now make R=1, S=0 Q=0 Q’=1 (Reset) Now make R=0, S=0 Q=0 Q’= 1 (No change) When both inputs are made zeros the previous state is kept! R=1,S=1 is not allowed! (illegal input; causes unstable state) R S R S Q Q

9 Page 9 Basic RS Latch  Timing Waveform Forbidden states: When both inputs become 1, Q=Q’=0 But if R=S=1 after that, a ‘race’ occurs. May switch to 0 or 1 Reset Hold Set Forbidden State ResetSet Forbidden State Race 100 R S Q Q

10 Page 10 Basic RS Latch Cross-Coupled NAND Gates Timing Waveform R S R S Q Q Reset Hold Set Forbidden State ResetSet Forbidden State Race R S Q Q Inputs are complemented, so the same behavour as previous NOR latch occurs.

11 Page 11 Basic RS Latch Truth Table Summary of R-S Nor- Latch Behavior Q hold 0 1 unstable S R S R Q 0 0 unstable hold Truth Table Summary of R-S NAND- Latch Behavior

12 Page 12 Basic RS Latch Function Table:Assume Q(t) is the current ‘state’ Next State = F(S, R, Current State) K-Map: Characteristic Equation: R SR X1 10X1 0 1 Q(t) S S(t) R(t) Q(t) Q(t+  ) X X HOLD RESET SET ILLEGAL } } } }

13 Page 13 Basic RS Latch with Clock Schematic: Timing Diagram: Clocked Latch: We want the state changes to occur only at the presence of clock pulses. R S Q Q Set Reset 100 S R EN Q Clock(EN)

14 Page 14 Basic RS Latch with Clock Another version: NAND implementation

15 Page 15 D Latch  D stands for data  We want to eliminate the unforbidden input case  Output will follow input

16 Page 16 D Latch  Timing Diagram  No hold state  Output follows the input Clock D Q

17 Page 17 JK Latch J-K Latch How to eliminate the forbidden state and keep hold state? Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle Characteristic Equation: Q+ = Q K + Q J J(t) K(t) Q(t) Q(t+  ) } } } } HOLD RESET SET TOGGLE S R Q Q J K Q Q

18 Page 18 JK Latch J-K Latch: Race Condition Race Condition! Single state change per clocking event is still desired. Solution: Master/Slave Flipflop Set Reset Toggle 100 J K Q Q

19 Page 19 Master-Slave Flip-Flop Two SR latches connected, master’s outputs are connected to slave’s inputs Master does not pass its state Y to slave until C=0 (Clock of slave will be 1) So output Q will take the value Y at the negative going edge of C. Master Slave

20 Page 20 Master-Slave Flip-Flop  Timing Diagram One’s catch: A level triggered catch that reflects at the output Incorrect behavior since S=0 at negative going edge

21 Page 21 Master-Slave Flip-Flop Master/Slave J-K Flipflop Master Stage Slave Stage Sample inputs while clock high Sample inputs while clock low Uses time to break feedback path from outputs to inputs! Correct Toggle Operation P J K Clk P Q SR Latch R S Q Q SR Latch R S Q Q Q Master outputs Slave outputs SetResetToggle 1's Catch100 J K Clk P Q P Q

22 Page 22 Edge-Triggered D Flip-Flop  Master slave still ‘pulse’ triggered because of the 1’s catching effect  Consider D type Master-slave FF ;Positive Edge triggered behavior-responds only at the edges

23 Page 23 Edge-Triggered D Flip-Flop  Timing Diagram: Does not catch the glitches C’ C D Y Q

24 Page 24 Sequential Switching Networks Bubble here for active 0 input device (negative edge triggered) Timing Diagram: Behavior the same unless input changes while the clock is high Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted Positive edge-triggered flip-flop Level-sensitive latch D Q ClkQ C D Q Q C D Q Q

25 Page 25 Sequential Switching Networks Definition of Terms Setup Time (Tsu) Clock: There is a timing "window" around the clocking event during which the input must remain stable and unchanged to ensure correct flip-flop operation There is a timing "window" around the clocking event during which the input must remain stable and unchanged to ensure correct flip-flop operation Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Input Clock T su T h Periodic Event, causes state of memory element to change rising edge, falling edge, high level, low level

26 Page 26 Sequential Switching Elements Typical Timing Specifications: Flipflops vs. Latches 74LS74 Positive Edge Triggered D Flipflop Setup time Hold time Minimum clock width Propagation delays (low to high, high to low, max and typical) All measurements are made from the clocking event that is, the rising edge of the clock T h 5 ns D Clk Q T su 20 ns T h 5 T w 25 ns T plh 25 ns 13 ns T su 20 ns T phl 40 ns 25 ns

27 Page 27 Sequential Switching Networks Typical Timing Specifications: Flipflops vs. Latches 74LS76 Transparent Latch Setup time Hold time Minimum Clock Width Propagation Delays: high to low, low to high, maximum, typical data to output clock to output Measurements from falling clock edge or rising or falling data edge T su 20 ns T h 5 T su 20 ns T h 5 T w 20 ns T plh C »Q 27 ns 15 ns T phl C »Q 25 ns 14 ns T plh D »Q 27 ns 15 ns T phl D »Q 16 ns 7 ns D Clk Q

28 Page 28 Sequential Switching Networks Edge-Triggered Flipflops 1's Catching: a glitch on the J or K inputs leads to a state change! forces designer to use hazard-free logic Solution: another edge-triggered logic, more complicated circuit Negative Edge-Triggered D flipflop 4-5 gate delays setup, hold times necessary to successfully latch the input Characteristic Equation: Q+ = D Negative edge-triggered FF when clock is high Q D Clk=1 R S 0 0 D Q D D Holds D when clock goes low Holds D when clock goes low

29 Page 29 Sequential Switching Network Edge-triggered Flipflops: Step-by-step analysis Negative edge-triggered FF when clock goes high-to-low data is latched Negative edge-triggered FF when clock is low data is held Q D Clk=0 R S D D Q D D D D Q D’ + D Clk=0 R S 0 0 D Q D D D

30 Page 30 Sequential Switching Networks Positive vs. Negative Edge Triggered Devices Positive Edge Triggered Inputs sampled on rising edge Outputs change after rising edge Negative Edge Triggered Inputs sampled on falling edge Outputs change after falling edge Toggle Flipflop Formed from J-K with both inputs wired together Positive edge- triggered FF Negative edge- triggered FF D Clk Qpos Qneg 100 Qpos Qneg

31 Page 31 Sequential Switching Networks Latches vs. Flipflops Input/Output Behavior of Latches and Flipflops Type When Inputs are Sampled When Outputs are Valid unclocked always propagation delay from latch input change level clock high propagation delay from sensitive (Tsu, Th around input change latch falling clock edge) positive edge clock lo-to-hi transition propagation delay from flipflop (Tsu, Th around rising edge of clock rising clock edge) negative edge clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) master/slave clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge)

32 Page 32 Flip-Flop Input Configurations  There are four basic FF input configurations  SR  JK  D  T

33 Page 33 The SR Flip-Flop S(t) R(t) Q(t) Q(t+  ) X X HOLD RESET SET ILLEGAL } } } } Characteristic Equation: Characteristic Table: Q Q S C PR CL R PR: Asynchronous preset CL: Asynchronous clear Available in most FF’s

34 Page 34 The JK Flip-Flop J(t) K(t) Q(t) Q(t+  ) } } } } HOLD RESET SET TOGGLE Characteristic Equation: Q+ = Q K + Q J Characteristic Table: Q Q J C PR CL K

35 Page 35 The D Flip-Flop D(t) Q(t) Q(t+  ) } } RESET SET Characteristic Equation: Q+ = D Characteristic Table: Q Q D C PR CL

36 Page 36 The T Flip-Flop T(t) Q(t) Q(t+  ) } } HOLD TOGGLE Characteristic Equation: Q+ = D  Q Characteristic Table: Q Q T C PR CL

37 Page 37 Realizing Circuits with Different Flipflops Characteristic Equations R-S: D: J-K: T: Q+ = S + R Q Q+ = D Q+ = J Q + K Q Q+ = T Q + T Q Derived from the K-maps for Q+ = ƒ(Inputs, Q) E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q Implementing One FF in Terms of Another D implemented with J-K J-K implemented with D D Q J K C Q Q J C K J K Q Q D C

38 Page 38 Realizing Circuits with Different Flipflops Design Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? Implementing D FF with a J-K FF: 1) Start with K-map of Q+ = ƒ(D, Q) 2) Create K-maps for J and K with same inputs (D, Q) 3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map E.g., D = Q= 0, Q+ = 0 then J = 0, K = X D T Q Q S X R X K X X 1 0 J 0 1 X X D Q + =D Q D XX 10 K =D D 01 XX J =D Q Q

39 Page 39 Realizing Circuits with Different Flipflops Implementing J-K FF with a D FF: Design Procedure (Continued) 1) K-Map of Q+ = F(J, K, Q) 2,3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple! Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF J K JK Q Q + =D =JQ +KQ 0 1

40 Page 40 Timing Methodology - Overview  Set of rules for interconnecting components and clocks  When followed, guarantee proper operation of system  Correct Timing:  (1) correct inputs, with respect to time, are provided to the FFs  (2) no FF changes more than once per clocking event

41 Page 41 Timing Methodologies Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register New value to first stage while second stage obtains current value of first stage Correct Operation, assuming positive edge triggered FF In Q 0 Q 1 Clk 100 IN CLK Q0 Q1 Q Q D C Q Q D C

42 Page 42 Timing Methodologies Cascaded Flipflops and Setup/Hold/Propagation Delays Why this works: Propagation delays far exceed hold times; This guarantees following stage will latch current value before it is replaced by new value Assumes infinitely fast distribution of the clock(no delays in clock) Timing constraints guarantee proper operation of cascaded components Timing constraints guarantee proper operation of cascaded components T su 20 ns T plh 13 ns T h 5 ns T su 20 ns T plh 13 ns T h 5 ns In Clk Q 0 Q 1

43 Page 43 Realizing Circuits with Different Kinds of FFs Choosing a Flipflop  R-S Clocked Latch:  used as storage element in narrow width clocked systems its use is not recommended!  however, fundamental building block of other flipflop types  J-K Flipflop:  versatile building block  can be used to implement D and T FFs  usually requires least amount of logic to implement ƒ(In,Q,Q+) but has two inputs with increased wiring complexity  because of 1's catching, never use master/slave J-K FFs; edge- triggered varieties exist

44 Page 44 Realizing Circuits with Different Kinds of FFs Choosing a Flipflop  D Flipflop:  minimizes wires, much preferred in VLSI technologies  simplest design technique  best choice for storage registers  T Flipflops:  don't really exist, constructed from J-K FFs  usually best choice for implementing counters  Preset and Clear inputs highly desirable!!


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