2Sequential Logic Finite State Machine (FSM) Pipelined System 2 storage mechanisms:Positive feedback (SRAM)Charge-based (DRAM)
3Naming Conventions In our textbook: a latch is Level-sensitive flip-flopa register is Edge-triggered flip-flopThere are many different naming conventionsFor instance, many books call Edge-triggered elements flip-flops (asynchronous JK, SR) This leads to confusion
4Latch v.s. Register Latch stores data when clock is low (or high) stores data when clock rises (on edges)DQDQClkClkClkClkDDQQ
6Latch-Based Design N latch is transparent when f = 0; hold when f = 1 P latch is transparent when f = 1; hold when f = 0ffNPLogicLatchLatchLogic
7Timing DefinitionstCLKDc-qholdsuQDATASTABLERegisterCLKDQ(a) Setup time (T_su): the time before the clock edge that the D input has to be stable(b) Hold time (T_hold): the time after tue clock edge that the D input has to main stable(c) Clock-to-Q delay (Tc-q): the delay from the positive clock input to the new value of the Q output.
25Making a Dynamic Latch Pseudo-Static Adding a weak feedback inverter
26Clocked CMOS (C2MOS)Clock1MasterEvaluateHoldSlaveHigh-impedance: HoldOutputPrevious value stored in CL2New Value of CL1“Keepers” can be added to make circuit pseudo-static
27Insensitive to Clock-Overlap DDDDDDDDMMMM2626MM48XXDQDQ1M1M37MMMM1515(a) (0-0) overlap(b) (1-1) overlap
28True Single-Phase Clocked Register (TSPC) Positive latch(transparent when CLK= 1)Negative latch(transparent when CLK= 0)A register can be constructed by cascading Positive andNegative Latches 12 transistors are used!
29Including Logic in TSPC Example: logic inside the latchAND latch
30Pipelined TSPC CMOS System Compared with NORA CMOS, we need two extra transistors per stage. But we can operate at a true singe-phase clock signal.Very attractive from system-design point of view.
43Example of NORA-CMOS (II) NOR2 + INV = OR2(Dynamic + Static Stages)
44SummarySequential circuits need good latches and registers for speed performance.Dynamic circuits can realize the pipelined system in a very efficient and compact way. But it should be designed with extreme care.Current trend is NOT to use dynamic CMOS for normal-speed operations good for design, maintain, and verification.