Sequential Logic (1)Finite State Machine (FSM) (2)Pipelined System 2 storage mechanisms: - Positive feedback (SRAM) - Charge-based (DRAM)
Naming Conventions In our textbook: a latch is Level-sensitive flip-flop a register is Edge-triggered flip-flop There are many different naming conventions For instance, many books call Edge- triggered elements flip-flops (asynchronous JK, SR) This leads to confusion
Latch v.s. Register Latch stores data when clock is low (or high) D Clk Q D Q Register stores data when clock rises (on edges) Clk D D QQ
Latches transparent hold
Latch-Based Design N latch is transparent when = 0; hold when = 1 P latch is transparent when = 1; hold when = 0 N Latch Logic P Latch
Timing Definitions t CLK t D t c - q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ (a) Setup time (T_su): the time before the clock edge that the D input has to be stable (b) Hold time (T_hold): the time after tue clock edge that the D input has to main stable (c) Clock-to-Q delay (Tc-q): the delay from the positive clock input to the new value of the Q output.
Characterizing Timing Clk DQ t C-Q-Q DQ t C-Q-Q t D-Q-Q Register Latch
Maximum Clock Frequency Also: t cdreg + t cdlogic >= t hold t cd : Contamination Delay = Minimum delay t clk-Q + t p,comb + t setup <= T CLK T t clk-Q + t p,comb + t setup
Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called “master-slave latch Pair “ Negative Latch Positive Latch MasterSlave
Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK
SR Flip-Flop: Cross-Coupled Pairs Forbidden State QRSQ Q00Q S Q R Q Cross-coupled NORs S R Q Q NOR-based Set-Reset Flop-Flop Cross-coupled NANDs
Clocked NOR-based SR Flip-Flop Added Clock Control This asynchronous SR FF is NOT used in datapaths any more, but is a basic building memory cell S Q R Q Cross-coupled NORs
Sizing Issues Output voltage dependence on transistor width Transient response
Storage Mechanisms D CLK Q Dynamic (charge-based) Static
Clock Overlap T 0-0 : T 1 and T 2 on Race Condition
Making a Dynamic Latch Pseudo-Static Adding a weak feedback inverter
Clocked CMOS (C 2 MOS) “Keepers” can be added to make circuit pseudo-static Clock01 MasterEvaluateHold SlaveHigh- impedance : Hold Evaluate OutputPrevious value stored in C L2 New Value of C L1
Insensitive to Clock-Overlap M 1 DQ M 4 M 2 00 V DD X M 5 M 8 M 6 V (a) (0-0) overlap M 3 M 1 DQ M 2 1 V DD X M 7 1 M 5 M 6 V (b) (1-1) overlap
True Single-Phase Clocked Register (TSPC) Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) A register can be constructed by cascading Positive and Negative Latches 12 transistors are used!
Including Logic in TSPC AND latch Example: logic inside the latch
Pipelined TSPC CMOS System (a)Compared with NORA CMOS, we need two extra transistors per stage. But we can operate at a true singe-phase clock signal. (b)Very attractive from system-design point of view.
Positive Edge-triggered Register in TSPC
TSPC-based Positive Edge-Triggered DFF From Referenced Textbooks:  “CMOS Integrated Circuits: Analysis and Design,” 3 rd Ed., by Sung-Mo Kang and Yusuf Leblebici, McGraw-Hill, 2003.
Pipelined Systems using Dynamic CMOS Circuits
Pipelining Reference Pipelined T_(non-pipe) = 3 x T_(pipeline)
Pipelining At the expense of “Latency (input-to-output delay)” Not good for interactive communicaitons
Latch-Based Pipeline Hold F Hold G Be careful of Race!
Review of NP-Domino Logic
NP-Domino Logic Example
NORA CMOS (a)Evaluation at Phi=1 (b)Evaluation at Phi=0 (c)Pipelined NORA CMOS system
Latch-based Pipeline using C2MOS Race-free as long as function F (implemented by static logic) between the Latches are Non-inverting!
Potential Race Condition during 0-0 (if F is inverting)
Example of NORA-CMOS (I)
Example of NORA-CMOS (II) NOR2 + INV = OR2 (Dynamic + Static Stages)
Summary Sequential circuits need good latches and registers for speed performance. Dynamic circuits can realize the pipelined system in a very efficient and compact way. But it should be designed with extreme care. Current trend is NOT to use dynamic CMOS for normal-speed operations good for design, maintain, and verification.