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Chapter 7 Designing Sequential Logic Circuits Rev 1.0: 05/11/03 1.1: 5/23/03 1.2: 5/30/03.

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Presentation on theme: "Chapter 7 Designing Sequential Logic Circuits Rev 1.0: 05/11/03 1.1: 5/23/03 1.2: 5/30/03."— Presentation transcript:

1 Chapter 7 Designing Sequential Logic Circuits Rev 1.0: 05/11/03 1.1: 5/23/03 1.2: 5/30/03

2 Sequential Logic (1)Finite State Machine (FSM) (2)Pipelined System 2 storage mechanisms: - Positive feedback (SRAM) - Charge-based (DRAM)

3 Naming Conventions  In our textbook:  a latch is Level-sensitive flip-flop  a register is Edge-triggered flip-flop  There are many different naming conventions  For instance, many books call Edge- triggered elements flip-flops (asynchronous JK, SR)  This leads to confusion

4 Latch v.s. Register  Latch stores data when clock is low (or high) D Clk Q D Q  Register stores data when clock rises (on edges) Clk D D QQ

5 Latches transparent hold

6 Latch-Based Design N latch is transparent when  = 0; hold when  = 1 P latch is transparent when  = 1; hold when  = 0 N Latch Logic P Latch  

7 Timing Definitions t CLK t D t c - q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ (a) Setup time (T_su): the time before the clock edge that the D input has to be stable (b) Hold time (T_hold): the time after tue clock edge that the D input has to main stable (c) Clock-to-Q delay (Tc-q): the delay from the positive clock input to the new value of the Q output.

8 Characterizing Timing Clk DQ t C-Q-Q DQ t C-Q-Q t D-Q-Q Register Latch

9 Maximum Clock Frequency Also: t cdreg + t cdlogic >= t hold t cd : Contamination Delay = Minimum delay t clk-Q + t p,comb + t setup <= T CLK T t clk-Q + t p,comb + t setup

10 Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

11 Mux-Based Latch

12 CLK Q M Q M NMOS only Non-overlapping clocks

13 Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

14 Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called “master-slave latch Pair “ Negative Latch Positive Latch MasterSlave

15 Master-Slave Register Multiplexer-based latch pair

16 Setup Time of MS-Register I 2 -T 2 : I 2 output to T 2 Check input of T2 and output of T2 are the same

17 Clk-Q Delay D Q CLK 20.5 1.5 2.5 t c- q(lh) 0.511.522.50 time, nsec Volts t c- q(hl)

18 Reduced Clock Load Master-Slave Register c.f: 8 Clock loads in Mater-Slave Register Design

19 Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK

20 SR Flip-Flop: Cross-Coupled Pairs Forbidden State QRSQ Q00Q 1010 0101 0110 S Q R Q Cross-coupled NORs S R Q Q NOR-based Set-Reset Flop-Flop Cross-coupled NANDs

21 Clocked NOR-based SR Flip-Flop Added Clock Control This asynchronous SR FF is NOT used in datapaths any more, but is a basic building memory cell S Q R Q Cross-coupled NORs

22 Sizing Issues Output voltage dependence on transistor width Transient response

23 Storage Mechanisms D CLK Q Dynamic (charge-based) Static

24 Clock Overlap T 0-0 : T 1 and T 2 on  Race Condition

25 Making a Dynamic Latch Pseudo-Static Adding a weak feedback inverter

26 Clocked CMOS (C 2 MOS) “Keepers” can be added to make circuit pseudo-static Clock01 MasterEvaluateHold SlaveHigh- impedance : Hold Evaluate OutputPrevious value stored in C L2 New Value of C L1

27 Insensitive to Clock-Overlap M 1 DQ M 4 M 2 00 V DD X M 5 M 8 M 6 V (a) (0-0) overlap M 3 M 1 DQ M 2 1 V DD X M 7 1 M 5 M 6 V (b) (1-1) overlap

28 True Single-Phase Clocked Register (TSPC) Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) A register can be constructed by cascading Positive and Negative Latches  12 transistors are used!

29 Including Logic in TSPC AND latch Example: logic inside the latch

30 Pipelined TSPC CMOS System (a)Compared with NORA CMOS, we need two extra transistors per stage. But we can operate at a true singe-phase clock signal. (b)Very attractive from system-design point of view.

31 Positive Edge-triggered Register in TSPC

32 TSPC-based Positive Edge-Triggered DFF From Referenced Textbooks: [1] “CMOS Integrated Circuits: Analysis and Design,” 3 rd Ed., by Sung-Mo Kang and Yusuf Leblebici, McGraw-Hill, 2003.

33 Pipelined Systems using Dynamic CMOS Circuits

34 Pipelining Reference Pipelined T_(non-pipe) = 3 x T_(pipeline)

35 Pipelining At the expense of “Latency (input-to-output delay)”  Not good for interactive communicaitons

36 Latch-Based Pipeline Hold F Hold G Be careful of Race!

37 Review of NP-Domino Logic

38 NP-Domino Logic Example

39 NORA CMOS (a)Evaluation at Phi=1 (b)Evaluation at Phi=0 (c)Pipelined NORA CMOS system

40 Latch-based Pipeline using C2MOS Race-free as long as function F (implemented by static logic) between the Latches are Non-inverting!

41 Potential Race Condition during 0-0 (if F is inverting)

42 Example of NORA-CMOS (I)

43 Example of NORA-CMOS (II) NOR2 + INV = OR2 (Dynamic + Static Stages)

44 Summary  Sequential circuits need good latches and registers for speed performance.  Dynamic circuits can realize the pipelined system in a very efficient and compact way. But it should be designed with extreme care.  Current trend is NOT to use dynamic CMOS for normal-speed operations  good for design, maintain, and verification.

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