 # 1 CS 151: Digital Design Chapter 5: Sequential Circuits 5-3: Flip-Flops I.

## Presentation on theme: "1 CS 151: Digital Design Chapter 5: Sequential Circuits 5-3: Flip-Flops I."— Presentation transcript:

1 CS 151: Digital Design Chapter 5: Sequential Circuits 5-3: Flip-Flops I

CS 151 2 Flip-Flops The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Standard symbols for storage elements Direct inputs to flip-flops Flip-flop timing

CS 151 3 The Latch Timing Problem In a sequential circuit, paths may exist through combinational logic:  From one storage element to another  From a storage element back to the same storage element The combinational logic between a latch output and a latch input may be as simple as an interconnect For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 1

CS 151 4 The Latch Timing Problem (continued) Consider the following circuit: Suppose that initially Y = 0. As long as C = 1, the value of Y continues to change! The changes are based on the delay present on the loop through the connection from Y back to Y. This behavior is clearly unacceptable. Desired behavior: Y changes only once per clock pulse Clock Y C D Q Q Y

CS 151 5 The Latch Timing Problem (continued) A solution to the latch timing problem is to break the closed path from Y to Y within the storage element The commonly-used, path-breaking solutions replace the clocked D-latch with:  a master-slave flip-flop  an edge-triggered flip-flop

CS 151 6 Consists of two clocked S-R latches in series with the clock on the second latch inverted The input is observed by the first latch with C = 1 The output is changed by the second latch with C = 0 The path from input to output is broken by the difference in clocking values (C = 1 and C = 0). The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur. C S R Q Q C R Q Q C S R Q S Q S-R Master-Slave Flip-Flop Master Slave Y

CS 151 7 S is set to 1 C is set to 1 Y is set to 1 Q remains unchanged Logic Simulation Assume all gates have 1ns gate delay

CS 151 8 S returns to 0 C is 0 Q copies value of Y Y is unchanged (1) Logic Simulation

CS 151 9 R is 1 If C is set to 1 Y changes to 0 Q remains unchanged Logic Simulation

CS 151 10 R is 1 When C is 0 Q copies the value of Y Y is unchanged (0) Logic Simulation

CS 151 11 1 ’ s Catching Behavior S sets to 1, R,C are 0 When a pulse appears, master latch “catches” the 1 on S and sets it’s output Y. Q remains unchanged. pulse-triggered S-R Master Slave flip-flop is said to be pulse-triggered, since it can respond to input values anytime during its clock pulse.

CS 151 12 1 ’ s Catching Behavior – Cont. S goes back to 0, A narrow 1 appears on R, Pulse on C still present Master responds to the 1 on R and changes Y back to 0. Q remains unchanged.

CS 151 13 1 ’ s Catching Behavior – Cont. C changes to 0 Slave copies value on Y  Q still 0. In general, the “correct” response is assumed to be the response to the input values when the clock goes to 0. So, in this case, the response is correct.

CS 151 14 1 ’ s Catching Behavior – Cont. A narrow 1 appears on S, Pulse on C active Master sets, Q still 0.

CS 151 15 1 ’ s Catching Behavior – Cont. C changes to 0 Slave copies value on Y  Q sets too. Recall: the “correct” response is assumed to be the response to the input values when the clock goes to 0. 1. Before the pulse appeared, Q was 0. 2. R and S were both low before the pulse returned to 0. 3. Then, Q should store a 0. So, in this case, the response is not correct.

CS 151 16 Note that what caused the erroneous state in the latter case was the 0 input on both S and R, which caused storing an “expired” input to the slave… How can we solve this? Flip-Flop Analysis

CS 151 17 Flip-Flop Solution Use edge-triggering instead of pulse-triggering (master-slave) An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal  Positive-edge (0-to-1 transition)  Negative-edge (1-to-0 transition) Edge-triggered flip-flops can be built directly at the electronic circuit level, or A master-slave D flip-flop which also exhibits edge- triggered behavior can be used.

CS 151 18 Edge-Triggered D Flip-Flop The edge-triggered D flip-flop is the same as the master- slave D flip-flop It can be formed by:  Replacing the first clocked S-R latch with a clocked D latch or  Adding a D input and inverter to a master-slave S-R flip-flop The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present with D replacing S and R inputs The change of the D flip-flop output is associated with the negative edge at the end of the pulse It is called a negative-edge triggered flip-flop C S R Q Q C Q Q C D Q D Q

CS 151 19 Positive-Edge Triggered D Flip-Flop Formed by adding inverter to clock input Q changes to the value on D applied at the positive clock edge within timing constraints to be specified Our choice as the standard flip-flop for most sequential circuits C S R Q Q C Q Q C D Q D Q 0 1 0 Y=D 11 0 Y

Download ppt "1 CS 151: Digital Design Chapter 5: Sequential Circuits 5-3: Flip-Flops I."

Similar presentations