EE415 VLSI Design Sequential Logic [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design Project Presentations What to include in presentation? Reason for choosing the design Final/Intended application Design constraints What it does/How it works Simulations!, Simulations!!, Simulations!!! Layout Post-layout simulations! Achieved goal? Unexpected glitches? Future work Contrast proposed schedule with actual schedule

EE415 VLSI Design Sequential Logic 2 storage mechanisms positive feedback charge-based COMBINATIONAL LOGIC Registers Outputs Next state CLK QD Current State Inputs

EE415 VLSI Design Meta-Stability Gain should be larger than 1 in the transition region

EE415 VLSI Design Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

EE415 VLSI Design Mux-Based Latch NMOS onlyNon-overlapping clocks D

EE415 VLSI Design Mux-Based Latch

EE415 VLSI Design Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

EE415 VLSI Design Reduced Clock Load Master-Slave Register

EE415 VLSI Design Avoid Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK

EE415 VLSI Design Storage Mechanisms D CLK Q Dynamic (charge-based) Static Very fast Was popular, now too risky

EE415 VLSI Design Making a Dynamic Latch Pseudo-Static Weak inverter

EE415 VLSI Design SR-Flip Flop Q S R Q S R QQ 0 1 0 1 0 0 1 1 Q 1 0 0 Q 0 1 0 S R Q Q Q S R Q S R Q Q 1 0 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1 Forbidden State S Q R Q

EE415 VLSI Design Cross-Coupled NOR Cross-coupled NORs Added clock This is not used in datapaths any more, but is a basic building memory cell Transistors M5-M8 are wider to switch the state S Q R Q

EE415 VLSI Design Sizing Issues Output voltage dependence on transistor width Transient response For various W/L 5 and 6

EE415 VLSI Design Naming Conventions l In our text: » a latch is level sensitive » a register is edge-triggered l There are many different naming conventions »For instance, many books call edge- triggered elements flip-flops »This leads to confusion however

EE415 VLSI Design Latch versus Register  Latch stores data when clock is low D Clk Q D Q l Register stores data when clock rises Clk D D QQ Falls with dataFalls with clock

EE415 VLSI Design Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

EE415 VLSI Design Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

EE415 VLSI Design Master-Slave Register Multiplexer-based latch pair

EE415 VLSI Design Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ Propagation delay time affects the clock period Set-up and hold times are needed to produce a stable output

EE415 VLSI Design Characterizing Timing Register Latch Clk DQ t C2Q DQ t C2Q t D2Q

EE415 VLSI Design Maximum Clock Frequency Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay t clk-Q + t p,comb + t setup = T Minimum clock period decides - the maximum operating frequency of a sequential circuit

EE415 VLSI Design Clk-Q Delay D Clk Q

EE415 VLSI Design Timing of Master-Slave Register In the multiplexer-based latch pair assume that propagation delays of inverters and transmission gates are t pd_inv and t pd_tx The setup time states how long before the rising edge of CLK data D must be stable. D has to propagate through I 1, T 1, I 3, and I 4 before the rising edge of CLK, so t setup =3 t pd_inv +t pd_tx The propagation delay is the time to propagate signal from Q M to Q. Since the output I 4 is valid before the rising edge of the clock, so t c-q =t pd_tx +t pd_inv The hold time (time for the input to be stable after rising edge of the clock) is 0 since D and clock are delayed by the same amount before reaching the T 1 gate, so a change of D after rising edge of the clock will reach T 1 after it is shut down and will not affect its output. Q M Q D CLK T 2 I 2 T 1 I 1 I 3 T 4 I 5 T 3 I 4 I 6

EE415 VLSI Design Setup Time Output failure = =

EE415 VLSI Design More Precise Setup Time Setup and hold times defined when delay increases by 5% delay

EE415 VLSI Design Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

EE415 VLSI Design Setup/Hold Time Illustrations Hold-1 case 0

EE415 VLSI Design Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static

EE415 VLSI Design Insensitive to Clock-Overlap M 1 DQ M 4 M 2 00 V DD X M 5 M 8 M 6 V (a) (0-0) overlap M 3 M 1 DQ M 2 1 V DD X M 7 1 M 5 M 6 V (b) (1-1) overlap

EE415 VLSI Design Other Latches/Registers: TSPC Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) Only single phase clocks are used. When  is high the latch is in the evaluate mode. When  is low the latch is in hold-mode.

EE415 VLSI Design Including Logic in TSPC AND latch Example: logic inside the latch

EE415 VLSI Design TSPC Register

EE415 VLSI Design Master-Slave Flip-flops

EE415 VLSI Design Pulse-Triggered Latches An Alternative Approach Master-Slave Latches D Clk QD Q Data D Clk Q Data Pulse-Triggered Latch L1L2L Ways to design an edge-triggered sequential cell: Need to generate the glitch pulse

EE415 VLSI Design Pulsed Latches

EE415 VLSI Design Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

EE415 VLSI Design Hybrid Latch-FF Timing Data not properly captured due to insufficient hold time

EE415 VLSI Design Pipelining Reference Pipelined

EE415 VLSI Design Latch-Based Pipeline

EE415 VLSI Design Non-Bistable Sequential Circuits─ Schmitt Trigger VTC with hysteresis Restores signal slopes

EE415 VLSI Design Noise Suppression using Schmitt Trigger

EE415 VLSI Design CMOS Schmitt Trigger These transistors resist the change in the X signal Move switching threshold of the first inverter V in M 2 M 1 V DD X V out M 4 M 3

EE415 VLSI Design CMOS Schmitt Trigger Increasing kn/kp ratio decreases the logical switching threshold If V in =0 the V out (connected to M 4 ) is also zero So effectively the input is connected to M 2 and M 4 in parallel This increases kp and the switching threshold If V in =0 the situation is reversed and kn increases reducing the switching threshold

EE415 VLSI Design Schmitt Trigger Simulated VTC 2.5 V out (V) V M2 V M1 V in (V) Voltage-transfer characteristics with hysteresis.The effect of varying the ratio of the PMOS deviceM 4. The width isk* 0.5 m. m 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5 k = 2 k = 3 k = 4 k = 1 V in (V) 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5 V out (V)

EE415 VLSI Design CMOS Schmitt Trigger (2) With input low and output high X is charged to V DD –V th M 2 is cutoff until the input is larger than V X +V th With output being pulled down M 5 is cut off and the output transition is very rapid This delays transition from high to low values on the output. Symmetrical analysis can be performed for low to high output transition

EE415 VLSI Design Multivibrator Circuits

EE415 VLSI Design Transition-Triggered Monostable DELAY t d In Out t d

EE415 VLSI Design Monostable Trigger (RC-based) RC delay regulates the width of the generated pulse V DD In Out A B C R In B Out t V M t 2 t 1 (a) Trigger circuit. (b) Waveforms.

EE415 VLSI Design Astable Multivibrators (Oscillators)

EE415 VLSI Design Relaxation Oscillator Out 2 CR 1 Int I1 I2 T = 2 (log3)RC

EE415 VLSI Design Voltage Controller Oscillator (VCO) Current I ref is a quadratic function of V contr This effects the delay time

EE415 VLSI Design Differential Delay Element and VCO in 2 two stage VCO v 1 v 2 v 3 v 4 V ctrl V o 2 V o 1 in 1 delay cell simulated waveforms of 2-stage VCO

EE415 VLSI Design JK- Flip Flop S R Q Q Q J K  J n K n Q n+1 0 0 1 1 0 1 0 1 Q n 0 1 Q n (c) Q (a) Q J K Q (b)  Problem – if JK flip-flop in a toggle state (J=K=1) can flip again For instance when Q=1, and J=K=1, then only R goes low and and Q changes to 0. If the clock is still high, the feedback disables K and enables J and FF changes its output again For clock=0 S=R=1 and FF maintains its previous state When J=K=1 then S=Q and FF toggles S R Q Q 1 0 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1

EE415 VLSI Design Other Flip-Flops Q J K Q  T  Q J K Q  D Q Q  TQ Q  D Toggle Flip-Flop Delay Flip-Flop (D-latch)

EE415 VLSI Design Race Problem Q Q  D 1 t t t loop  Signal can race around during  = 1

EE415 VLSI Design Master-Slave Flip-Flop S R Q Q Q Q S R Q Q J K  MASTER SLAVE Q J K Q  PRESET CLEAR SI RI Master transmits the signal to the output during the high clock phase and slave is waiting for the clock to change this prevents race conditions

EE415 VLSI Design Propagation Delay Based Edge-Trigger Circuit which produces a short output impulse used in edge triggered devices

EE415 VLSI Design Edge Triggered Flip-Flop No need for master-slave configuration

EE415 VLSI Design Sequential Logic [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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EE415 VLSI Design Sequential Logic [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Presentation on theme: "EE415 VLSI Design Sequential Logic [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]"— Presentation transcript:

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About project

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