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© Digital Integrated Circuits 2nd Sequential Circuits Designing Sequential Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

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© Digital Integrated Circuits 2nd Sequential Circuits Sequential Logic Combinational Logic State Clock Next State Current State Inputs Outputs 2 storage mechanisms: positive feedback charge-based

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© Digital Integrated Circuits 2nd Sequential Circuits Naming Conventions In the text: a latch is level sensitive a register is edge-triggered Many different naming conventions: flip-flops (level or edge?) Transparency? Dual edge/level

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© Digital Integrated Circuits 2nd Sequential Circuits Latch versus Register Latch- stores if clock is low transparent if clock is high D Clk Q D Q Register- stores if clock rises, never transparent (mostly) Clk D D QQ

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© Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Design N latch is transparent when = 0 P latch is transparent when = 1 N Latch Logic P Latch

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© Digital Integrated Circuits 2nd Sequential Circuits Timing Definitions t CLK t D t c lk2q t hold t setup t Q DATA STABLE DATA STABLE Register CLK DQ

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© Digital Integrated Circuits 2nd Sequential Circuits Maximum Clock Frequency Register LOGIC t P(comb) Timing Constraints: t clk2q + t p(comb) + t setup = T t cdreg + t cdlogic > t hold First Constraint ensures clock is slow enough that Registers sample correct value Second Constraint ensures that there is no path after the clock changes to alter the previously stored data

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© Digital Integrated Circuits 2nd Sequential Circuits Positive Feedback: Bi-Stability V i1 V o2 V o2 =V i1 V o1 =V i2 V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1 A,B Stable points C is unstable:(metastable) Feedback moves state to Stable points, eventually

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© Digital Integrated Circuits 2nd Sequential Circuits Writing a Static Latch D CLK D Use the clock to distinguish between the transparent and opaque states Converting into a MUX Forcing the state (can implement as NMOS-only)

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© Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

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© Digital Integrated Circuits 2nd Sequential Circuits Master-Slave Register Two opposite latches trigger on edge Also called master-slave latch pair CLK D Qm Q Q D CLK

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© Digital Integrated Circuits 2nd Sequential Circuits Clk-Q Delay CLK D Q T clk-q Clock to Q delays are Different for rising and falling Transitions Use Worst Case – not Avg!

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© Digital Integrated Circuits 2nd Sequential Circuits Setup Time (MS register) D CLK Q Qm D Q Setup = 0.21nS Passed D Setup = 0.20nS Failed to pass D

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© Digital Integrated Circuits 2nd Sequential Circuits Cross-Coupled Pairs NOR-based set-reset S R Q Q’ S0101S0101 R0011R QQ10-QQ10-

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© Digital Integrated Circuits 2nd Sequential Circuits Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic register memory cell

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© Digital Integrated Circuits 2nd Sequential Circuits Sizing Issues Output voltage dependence on transistor width Transient response Q’ (V) W/L (M5,M6) M2= W=0.5 W=0.7 W=0.8 W=1

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© Digital Integrated Circuits 2nd Sequential Circuits Storage Mechanisms D CLK Q Dynamic (charge-based) Static

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© Digital Integrated Circuits 2nd Sequential Circuits Making a Dynamic Latch Pseudo-Static

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

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© Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

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© Digital Integrated Circuits 2nd Sequential Circuits Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static

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© Digital Integrated Circuits 2nd Sequential Circuits Insensitive to Clock-Overlap M 1 DQ M 4 M 2 00 V DD X M 5 M 8 M 6 V (a) (0-0) overlap M 3 M 1 DQ M 2 1 V DD X M 7 1 M 5 M 6 V (b) (1-1) overlap

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© Digital Integrated Circuits 2nd Sequential Circuits Pipelining Reference Pipelined

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© Digital Integrated Circuits 2nd Sequential Circuits Other Latches/Registers: TSPC Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1)

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© Digital Integrated Circuits 2nd Sequential Circuits Pulse-Triggered Latches An Alternative Approach Master-Slave Latches D Clk QD Q Data D Clk Q Data Pulse-Triggered Latch L1L2L Ways to design an edge-triggered sequential cell:

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© Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Pipeline CLK ~CLK CLK F G FG

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© Digital Integrated Circuits 2nd Sequential Circuits Non-Bistable Sequential Circuits─ Schmitt Trigger VTC with hysteresis Restores signal slopes

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© Digital Integrated Circuits 2nd Sequential Circuits Noise Suppression: Schmitt Trigger

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© Digital Integrated Circuits 2nd Sequential Circuits CMOS Schmitt Trigger Moves switching threshold of the first inverter

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© Digital Integrated Circuits 2nd Sequential Circuits Schmitt Trigger Simulated VTC 2.5 V X (V) V M2 V M1 V in (V) Voltage-transfer characteristics with hysteresis.The effect of varying the ratio of the PMOS deviceM 4. The width isk* 0.5 m. m V x (V) k = 2 k = 3 k = 4 k = 1 V in (V)

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© Digital Integrated Circuits 2nd Sequential Circuits CMOS Schmitt Trigger (2)

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© Digital Integrated Circuits 2nd Sequential Circuits Multivibrator Circuits

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© Digital Integrated Circuits 2nd Sequential Circuits Transition-Triggered Monostable

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© Digital Integrated Circuits 2nd Sequential Circuits Monostable Trigger (RC-based)

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© Digital Integrated Circuits 2nd Sequential Circuits Astable Multivibrators (Oscillators) 012N-1 Ring Oscillator simulated response of 5-stage oscillator

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© Digital Integrated Circuits 2nd Sequential Circuits Relaxation Oscillator

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© Digital Integrated Circuits 2nd Sequential Circuits Voltage Controller Oscillator (VCO)

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© Digital Integrated Circuits 2nd Sequential Circuits Differential Delay Element and VCO in 2 two stage VCO v 1 v 2 v 3 v 4 V ctrl V o 2 V o 1 in 1 delay cell simulated waveforms of 2-stage VCO

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© Digital Integrated Circuits 2nd Sequential Circuits Homework 7 1. A common way to characterize registers is to measure the timing aperture which is the total window in which transitions on data are not correctly output. This is done by making two clocks which are close, but not the same so that the relative phase drifts slowly with each cycle. Construct a pseudo-static master/slave flip-flop in SUE with the assumption that the input is driven by a unit inverter (2/1, min width nmos), the clock is driven by a 2x inverter. Optimize your designs to minimize the timing aperture (setup+hold) and clock to Q assuming the output load is 2 min inverters. Simulate your designs in SPICE and turn in both the designs (annotated schematics and spice results – plz. don’t waste paper!) 2. Do problem 1 again, with TSPC based flipflop. (High performance)

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