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Latches CS370 –Spring 2003 Section 4-2 Mano & Kime.

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Presentation on theme: "Latches CS370 –Spring 2003 Section 4-2 Mano & Kime."— Presentation transcript:

1 Latches CS370 –Spring 2003 Section 4-2 Mano & Kime

2 Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only on current input but also on past input values –Need some type of memory to remember the past input values

3 Circuits that we have learned so far Information Storing Circuits Timed “States”

4 Storing Information Buffers Inverters

5 Can’t change the stored value!

6 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand

7 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand

8 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand

9 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set

10 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store

11 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store

12 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store

13 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store 0 1 Reset

14 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store 0 1 Reset

15 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0

16 !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0

17 S-R Latches

18 S-R Latch Simulation

19 S - R Latch with a Clock Signal (Sequential)

20 S-R Latch !S !R Q !Q S R CLK S R CLK !S !R Q !Q Q 0 !Q 0 Store Reset Set Disallowed X X Q 0 !Q 0 Store

21

22 D Latch Q !Q CLK D !S !R S R S R CLK Q !Q Q 0 !Q 0 Store Reset Set Disallowed X X 0 Q 0 !Q 0 Store X 0 Q 0 !Q 0 D CLK Q !Q

23 D Latch Q !Q CLK D !S !R S R X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

24 D Latch CLK D Q E x y z x y z Does NOT latch z = z $ x = 0 $ 1 = 1 Latches on following edge of clock

25 D Latch CLK D Q E x y z x y z Does latch z = z $ x = 0 $ 1 = 1 Use narrow pulse If x remains high, successive clock pulses will toggle z

26 D Latch with Transmission Gates

27 D Flip-Flop X 0 Q 0 !Q 0 D NCK Q !Q Q !Q D !S !R S R CLK Pulse-narrowing circuit NCK X 0 Q 0 !Q 0 D CLK Q !Q

28 Pulse-Narrowing Circuit

29 D Flip-Flop CLK DQ !Q X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

30 D Flip-Flop CLK DQ !Q y CLK z pulse width setup time hold time propagation delay

31 SR Master-Slave Flip-Flop S R CLK Q !Q Q 0 !Q 0 Store Reset Set Disallowed X X 0 Q 0 !Q 0 Store

32 CLK K Q !Q J J-K Flip-Flop J K CLK Q !Q 0 0 Q 0 !Q Toggle X X 0 Q 0 !Q 0

33


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