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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 425 - VLSI Circuit Design Lecture 16 - Sequential.

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Presentation on theme: "Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 425 - VLSI Circuit Design Lecture 16 - Sequential."— Presentation transcript:

1 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 16 - Sequential Logic Spring 2007

2 ECE 425 Spring 2007Lecture 16 - Seq. Logic2 Announcements  Reading  Book:  Verilog Handout: , 5.6

3 ECE 425 Spring 2007Lecture 16 - Seq. Logic3 Where we are  Last Time:  Combinational Logic / Verilog ASIC Design  Today:  Sequential Logic

4 ECE 425 Spring 2007Lecture 16 - Seq. Logic4 Review: Combinational vs. Sequential Logic  Combinational Logic  Output depends on current input  Sequential Logic  Output depends on current input AND  Output depends on stored state current state next state

5 ECE 425 Spring 2007Lecture 16 - Seq. Logic5 Review: Memory Elements  Latch - "transparent" while enabled (level-sensitive)  Flip-flops - transfer data on active edge

6 ECE 425 Spring 2007Lecture 16 - Seq. Logic6 Review: Memory Element Timing  Setup time t su - time D must be stable before data transfer  Hold time t su - time D must be stable after transfer

7 ECE 425 Spring 2007Lecture 16 - Seq. Logic7 Static Storage Elements  Key circuit: cross-coupled inverters (or NOR gates)  Static storage - feedback preserves value while power is on  Avoided in CMOS due to large size, delay

8 ECE 425 Spring 2007Lecture 16 - Seq. Logic8 Aside: Regenerative Storage Elements  Two stable states  V o1 =L, V o2 =H  V o1 =H, V o2 =L  One metastable state  V o1 = V o2  Ugly characteristic: unbounded delay for recovery from metastable state Graphic source: J. Rabaey, Digital Integrated Circuits, © Prentice-Hall, 1996 Metastable point

9 ECE 425 Spring 2007Lecture 16 - Seq. Logic9 Simplest CMOS Latch: Dynamic Latch  When ø=1 (ø'=0) - latch enabled  charge/discharge C g on inverter input to "load"  output follows input changes - "transparent" operation  When ø=0 (ø'=1) - latch disabled  output uses stored value in C g  must use or rewrite value before charge in C g decays (~1ms) Parasitic Capacitance used for Storage

10 ECE 425 Spring 2007Lecture 16 - Seq. Logic10 Layout - Simple Dynamic Latch  Stick diagram  p-transistors in top  n-transistors in bottom  vertical ø, ø' lines allow creation of multiple-bit latches!

11 ECE 425 Spring 2007Lecture 16 - Seq. Logic11 Layout - Simple Dynamic Latch D Q’ V DD V SS ’’  Fig 5-4, p. 254

12 ECE 425 Spring 2007Lecture 16 - Seq. Logic12 Dynamic Latch Timing  Setup time t su : time to charge / discharge C g plus inverter prop delay  Hold time t h : "turn-off" time of transmission gate  Result of violating t su, t h window:  Capacitor C g not fully charged/discharged  Incorrect / Invalid output value

13 ECE 425 Spring 2007Lecture 16 - Seq. Logic13 Multiplexed Dynamic Latch  Multiple inputs D1, D2  A, B must never be 1 at same time

14 ECE 425 Spring 2007Lecture 16 - Seq. Logic14 Recirculating “Quasi-Static” Latch  Modes of operation:  LD High, ø Low: "transparent"  LD Low, ø Low: "opaque"  ø High: "recirculating" (LD must be Low here!)  Special considerations:  LD "qualified" by ø1  ø1, ø2 must not overlap  Problem: charge sharing when driving large load (fix: buffering) (q  1) - “Qualified” by  1(q  1)

15 ECE 425 Spring 2007Lecture 16 - Seq. Logic15 Clocked Inverter - A Latch Building Block  Combines inverter, transmission gate  Operation   =1: acts like normal inverter   =0: high impedance output  ,  ' placed closest to output for fast switching between modes

16 ECE 425 Spring 2007Lecture 16 - Seq. Logic16 Clocked-Inverter Latch  Operation  f=1 (f'=0): Inverter 1 "on", latch transparent  f=0 (f'=1): Inverter 2 "on", latch; recirculates

17 ECE 425 Spring 2007Lecture 16 - Seq. Logic17 Alternative: Regenerative Latch  Omit "clocked" p-transistors  Use feedback to regenerate values  in out

18 ECE 425 Spring 2007Lecture 16 - Seq. Logic18 Alternative: Clocked SR Latch  Alternative to "cross-coupled NOR" structure used in bipolar logic families  Fully static  Transistors must be carefully sized (Fig. 5-12, p. 260)

19 ECE 425 Spring 2007Lecture 16 - Seq. Logic19 Flip-Flops  Key difference: flip-flops are non-transparent  Output isolated from input except at clock edge  Types of flip-flops  Master-Slave ("pulse triggered")  Edge-Triggered

20 ECE 425 Spring 2007Lecture 16 - Seq. Logic20 Master-Slave Flip-Flops  Master stage:  transparent while ø high  disabled while ø low  Slave stage:  transparent while ø low  transparent while ø high  Q output changes on falling edge of ø

21 ECE 425 Spring 2007Lecture 16 - Seq. Logic21 Pseudo-Static Master-Slave FF

22 ECE 425 Spring 2007Lecture 16 - Seq. Logic22 Edge-Triggered Flip-Flops  Designed to respond only on clock edge  Positive Edge-Triggered: Rising Edge  Negative Edge-Triggered: Falling Edge  Approaches  Construct from master-slave flip-flop (see below)  Construct from static gates (see ECE 212) Positive Edge-Triggered Negative Edge-Triggered

23 ECE 425 Spring 2007Lecture 16 - Seq. Logic23 Dynamic Negative Edge-Triggered FF  Constructed using Clocked Inverters  Not sensitive to overlap (if clock edge rise/fall times "sufficiently small"  Often used for pipelineing latches (more later)

24 ECE 425 Spring 2007Lecture 16 - Seq. Logic24 Example: A Standard-Cell NETFF  MSU Standard Cell DFNF311 - Circuit Diagram

25 ECE 425 Spring 2007Lecture 16 - Seq. Logic25 Example: A Standard-Cell NETFF  Transistor Schematic

26 ECE 425 Spring 2007Lecture 16 - Seq. Logic26 Example - A Standard-Cell NETFF  MSU Standard cell DFNF311 - Layout

27 ECE 425 Spring 2007Lecture 16 - Seq. Logic27 Coming Up:  Clocking Disciplines  Sequential logic in Verilog HDL  FSM Design


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