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**Sequential MOS Logic Circuits**

A. Marzuki

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**Introduction Sequential Circuit Behavior of Bistable Elements**

SR Latch Circuit Clocked Latch and Flip Flop Circuits CMOS D-Latch and Edge-Triggered Flip-Flop

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**Classification of logic circuits based on temporal behaviour**

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Sequential circuit

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**BiStable simple analogy the energy function**

Voltage gain of inverters is larger than unity at unstable Point, a small voltage perturbation at the input of any of the inverters will be amplified, causing the operation point to move to one of the stable points. simple analogy the energy function P ( x ) could be the potential energy of some one-dimensional mechanical system. The gradient of P ( x ) is a “force”

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**Bistable At V01 = V02 Unstable condition**

where gm = (gmN + gmP ) : All four Transistor are in saturation Direction is determined by initial perturbation polarity. Output Expectation (exponential!!!)

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**Continue… Gate Capacitance >>> Drain Capacitance Gate Charges**

Derivative of small-signal gate voltages

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Continue… Combination above three equations

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Continue… Combination of two equation yields 2nd order differential equation Time behaviour of gate charge q1

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Continue…

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Continue…

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Continue… Assume ~ Large t

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SR Latch Circuit

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**Gate-level Schematic/Block Diagram.**

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Truth Table

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Operation Mode

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Capacitance

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**Circuit with Capacitance**

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Rise Time

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**Depletion Load nMOS (NOR2)**

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**CMOS SR Latch circuit (NAND2)**

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Gate Schematic(NAND)

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Truth Table

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**Depletion Load nMOS (NAND)**

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**Clocked Latch and Flip-Flop Circuits**

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**Sample Input-Output Waveforms**

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**AOI Implementation (NOR)**

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**Gate Schematic (NAND), active low**

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**Gate Schematic (NAND), active high**

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Partial Block Diagram

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Gate Schematic

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Block Diagram

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**All NAND Implementation**

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Detailed Truth Table J, K Compliments Q will go to J value at the next clock edge. J, K HIGH, the output will reverse its state after each clock pulse.

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NOR-based JK Latch

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AOI Realization(NOR)

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Toggle Switch

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**Master-Slave Flip Flop**

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**Master-Slave Flip Flop**

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**Master-Slave Flip Flop (NOR)**

CLK is HIGH MASTER is enable. Slave is disable and retains its previous state. CLK is LOW is disconnected while input of slaves are simultaneously coupled to the output of the slaves.

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**CMOS D-Latch and Edge-Triggered Flip Flop**

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CMOS Implementation

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**Simplified Schematic View**

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Timing Diagram

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**2nd CMOS Implementation**

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**CMOS –ve Edge-triggered**

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**Simulated Input-Output**

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Timing Violation

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Layout

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**CMOS +ve Edge-triggered**

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Timing Diagram

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References Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test, JENS U. HORSTMANN, JSSC, FEB 1989. S-M. Kang and Y. Leblebici ,CMOS Digital Integrated Circuits: Analysis and Design,, 3rd edition

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Designing Sequential Logic Circuits Ilam university.

Designing Sequential Logic Circuits Ilam university.

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