1. Integration through Wafer-level Packaging Approach
Dr. Kai Liu
STATS ChipPAC

2. Fan-Out WLP Process Similar to fc-package.
But more straightforward, and more integrated process.
No bumps and substrate involved-low profile possible.
Comparison of flip chip packaging and fan-out eWLB packaging.

3. FIWLP and FOWLP Similar to FIWLP after Recon wafers.
Recon wafer process involves:
Incoming wafer back-grinding, dicing, chip-placement and compress molding, and carrier de-bonding.

4. Two-die Integration in FOWLP
CMOS Die
IPD Die
Different Silicon-node IC dies with different die- thicknesses can be used.
Finer design rules allow smaller form-factors.
Excellent electrical performance.
Equivalent or slightly better thermal performance compared to fc-BGA.
eWLB with two dies. One is power amplifier die and another is IPD die.

5. Laminate Package and eWLB
Finer design rules.
Less layers needed.
Low-profile.
Excellent electrical performance.
Equivalent thermal performance compared to fc-BGA.
Illustration of eWLB approach (top) and fcBGA approach (bottom) for SiP.

6. Thin eWLB with Two Dies Exposed-die eWLB with two dies.
150um
310um
Exposed-die eWLB with two dies.
Thin profile for IoT and Wearable application.
eWLB body side can be um with package size up to 16x16mm.
Acceptable warpage performance.

7. Thin eWLB Performance
Package size: 6.0 x 7.0 x 0.2 mm (including micro ball height of 80um)- eWLB body size: 120um.
Used as interposer to translate very fine pitch (<100um) to um with micro balls).
Warpage about 90um for such very thin eWLB (120um).

8. eWLB with Laminate Interposer
eWLB as bottom package.
Laminate interposer as top package.
Vertical interconnections are made available through PCB-bar structures.
Interposer can have LC components. C to be implemented in periphery and L to be implemented in the middle if possible.
PCB Bar

9. Surface Roughness Comparison
Cu trace in laminate substrate is rough. TRMS of surface roughness can be as high as 3um.
Cu TRL in WLP process is very smooth. RMS of surface roughness can be as low as 0.3um.
Surface roughness has big impact on insertion loss for very high-frequency applications (>30GHz).
Laminate Substrate
eWLB with 3 RDL Layers

10. PoP Package for Milimeter -Wave Application
Antenna package stacked on to an eWLB
For >30 GHz applications, antenna size can be less than 10x10mm, which can be implemented in common packages.
EMI shielding is critical for antenna-in-package applications.

11. PoP Package for Milimeter -Wave Applications (cont’d)
PCB Bar
Double-side RDL allows implementing antenna and transceiver in one package.
PCB-bars are used for vertical interconnections.
PCB-bars can be used effectively for EMI shielding.
PoP with double side RDL

12. PoP Package for Milimeter -Wave Applications (cont’d)
Antenna pattern is made in bottom RDL.
Antenna ground is made in to RDL.
Separation is realized by properly selecting the PCB-bar height.
Shielding between antenna and transceiver is achieved PCB-bars.
Package including antenna and transceiver for mmWave applications.

13. Summary
Fan-out process is a more straightforward and more integrated process, than other packaging approaches.
Low profile and small form-factor can be achieved.
Excellent electrical performance, and equivalent thermal performance to fc-BGA.
eWLB suitable for very high frequency (mmWave) packaging with less metal insertion-loss and tighter process tolerance.
eWLB approach using double-side RDL with PCB- bars is attractive for mmWave antenna-in-package applications.