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Wafer Level Packaging: A Foundry Perspective Wafer level packaging (WLP) and customized electrical I/O schemes (TSV) have become mature technology platforms.

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Presentation on theme: "Wafer Level Packaging: A Foundry Perspective Wafer level packaging (WLP) and customized electrical I/O schemes (TSV) have become mature technology platforms."— Presentation transcript:

1 Wafer Level Packaging: A Foundry Perspective Wafer level packaging (WLP) and customized electrical I/O schemes (TSV) have become mature technology platforms.

2 WLP is generally customized to meet specific customer requirements:  Die Size  Temperature Budget  Materials Used  Hermiticity Requirements  Absolute Pressure  Specialized Packaging

3 Wafer Level Packaging Options  Low Temperature Metal Alloy Bond High Production Yields (99.1%) – based on dies and 592 wafers Low Temperature Bond (160 to 190 C) with High Reflow Temperature (> 500 C) Narrow Bond Line Width (50 to 100  m) Tightly Controlled Bond Line Thickness (+/- 5  m) Topography Tolerant (Up to 7000 A) High Bond Strength

4  Low Temperature Metal Alloy Bond (Continued) Electrically Conductive Hermetic Compatible across multiple substrates Hermiticity verified on a die by die basis by electrically probing in package thermistors

5  Low Temperature Metal Alloy Bond (Continued) The reliability of this bond technology was verified a number of time by independent laboratories.  96 hour autoclave at 2 ATM and 121 C  SF6 bombing for 1487 hours  Air bombing for 1295 hours at 2 ATM  Air bombing for 200 hours at 150 C  85 C / 85% RH exposure for 1262 hours

6  Glass Frit Bond Low cost Hermetic High vacuum (<1 mTorr) Bond line widths ~ 400  m Bond Temperature (400 C)  Compatible with getter activation Extremely Strong  Withstand 12,000 G acceleration loads

7  Glass Frit Bond (Continued) Topography tolerant Can go over active circuits  Providing the correct metallurgy is selected Well characterized reliability Wafer Aligner Wafer Bonder

8  Anodic Bonding Excellent technology for bonding silicon and glass wafers Low temperature (300 C) and low voltage (300 V) is now mature Hermetic Not topography tolerant Bond line widths ~200  m Bond strength similar to glass frit Excellent reliability characteristics

9  Silicon Fusion Bonding First demonstrated in 1986 and now very mature technology Enables the production of complex structures by combining by combining two or more patterned and etched wafers Bond is extremely strong and hermetic Wafers must be atomically clean and smooth Prior to bond a hydrophilization step is required but this is very predictable Main drawback, high post bond annealing temperatures (~ 1000 C)  Prohibits any metals

10  Au / Au Thermo-Compression Bond Hermetic Sputter deposited bond line ~ 50  m in width Bond temperature ~ 300 C Bond line loading > 5 MPa Not topography tolerant Bond strength not as high as glass frit but higher than eutectic Some commercial bonding systems cannot generate enough clamp force

11  Polymer bonding Not hermetic  Effective as a particulate contamination barrier and resistant to fluid penetration  Used widely in micro-fluidic circuits Low cost Lithographyically defined bond lines  Widths and heights can vary widely to suit various applications Bond temperature low (~ 200 C)

12  WLP Summary All six of the bond technologies reviewed are mature production worthy options Tens of thousands of successful bonds have demonstrated the value of wafer level packaging Sophisticated wafer bonding systems are manufactured by several companies  All of the discussed bonds can be performed on these systems Critical component in 3D packaging Allows integration of heterogeneous technologies Reduces packaging cost Allows package size reduction

13  WLP Summary (Continued) When choosing a bond technology various factors need to be considered:  Die size and design  Available bond line real estate  Die topography  Device temperature budget  Vacuum and hermiticity requirements  Die packaging environment  Bond line electrical conductivity or dielectric property considerations

14  Electrical I/O Configurations, Through Silicon Vias (TSV) Typical configuration, Solid Copper via with SiO2 insulation through one if the two wafers making up the bonded pair Lid Wafer and Device Cavity TSV Back Side Circuits And Bumps WLP Bond Line Note, the bond line can be patterned to be an electrical circuit

15  Electrical I/O Configurations, Through Silicon Vias (TSV) Typical RF performance data for TSV  Single via adds only ~0.01 bB of loss of loss at 6 GHz

16  Electrical I/O Configurations, Through Silicon Vias (TSV) Historically, the industry has struggled making TSV void free.  Recent process advances have overcome this problem  150,000 TSV in a 150 mm wafer with a via yield of 99.9%

17  Electrical I/O Configurations, Through Silicon Vias (TSV) There are specific via design rules that need to be followed 50 x 250um in Reliability testing 50 x 500um demonstrated

18  Electrical I/O Configurations, Through Silicon Vias (TSV) There is virtually no change in via resistance as a function of temperature cycling

19  Electrical I/O Configurations, Through Silicon Vias (TSV) Summary  Creation of metal filled vias is a mature high yielding process technology within the MEMS industry  TSV technology is the next logical step in providing vertical integration in the semiconductor market driven by space constraints in hand held mobile devices  TSV are a major component in 3D packaging

20  Electrical I/O Configurations, Through Silicon Vias (TSV) Summary (Continued)  Metal filled vias have the following attributes:  Low resistance (0.01 Ohms per via)  Low insertion loss for RF applications  A vehicle to allow die shrinkage  Can vary in diameter from 15 to 50um  Can go completely through a 500um wafer  Are electrically isolated from the silicon  Are compatible with high volume, low cost post wafer chip processing  Can be fabricated with a high via yield (99.96%)

21  Conclusion WLP Plus TSV The combination of these two technologies provide significant advantages to MEMS designers in the following areas:  Low pressure, low cost packaging  Low insertion loss electrical I/Os  Low resistance I/Os  Smaller chip sizes


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