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ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASE Flip-Chip Build-up Substrate Design Rules ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. Date : 2/12/2004.

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Presentation on theme: "ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASE Flip-Chip Build-up Substrate Design Rules ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. Date : 2/12/2004."— Presentation transcript:

1 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASE Flip-Chip Build-up Substrate Design Rules ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. Date : 2/12/2004 Rev. H

2 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC.  The Data needed for Design  Build Up Flip Chip lead time. Flip Chip Pad Design Rule. Fine Flip Chip Pitch Proposal – 200 / 150 um. Layout Rule for Build Up Layer. Layout Rule for Core Layer. Available Substrate Structure  Assembly Rule  Substrate Roadmap Content

3 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC.  Package type & Body size  Wafer thickness & Die size. Die orientation Including Pin 1 logo, die up or die down.. Die pad number, metal size & passivation opening.. UBM diameter. Solder bump height, pitch & composition.  Solder ball size, pitch, number, location.  Net list ( net name, coordinates and ball no. )  Special Requirement (Thermal, Electrical or Others) Design Information needed

4 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. Build-Up Design Cycle-time & Delivery Design Cycle Time : Flip Chip BGA 7 days >>> 5 days Built-up Substrate 1st Article Delivery: (After Vendor drawing confirm) Lead Time General Hot-Run layers : 6.0 wk 4.5 wk layers : 6.5 wk 5.0 wk layers : 7.0 wk 5.5 wk layers : 8.0 wk 6.0 wk For ASEMT Only: Lead Time General Hot-Run *Super Hot-Run layers : 4.0 wk3.5 wk 3.0 wk layers : 4.5 wk 4.0 wk 3.5 wk layers : 5.0 wk 4.5 wk 4.0 wk layers : 6.0 wk 5.0 wk 4.5 wk * Maximum 1K units (per substrate per order)

5 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. 100 Item Min. Solder resist opening C4 pad pitch ( no line pass ) Min. S/M Coverage 25 Risk 180 # Normal C4 pad pitch ( pass one lines ) Trace on neck 25 um Solder Resist Solder Bump SMD with Solder Flip Chip Pad Design Rule Solder Resist Solder Bump Bump on Via (Filled) Advance 200

6 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. **200 um Bump Pitch for One Line Pass Proposal for fine flip chip pitch-I Solder Resist Solder Bump B A C F G

7 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. **150 um Bump Pitch for One Line Pass Proposal for fine flip chip pitch-II 1st layer 2nd layer Solder Resist Solder Bump B A C E G H F D For 150um proposal, Need to Control Die Bump UBM Diameter: 70 ~ 90 um

8 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. Layout Rule for Build Up Layer A B C A D C B E GH Bump Local Area F

9 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. F B A E C AB D Layout Rule for Core Layer

10 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. Number of build up layer 1, 2, 3, 4 / Side 2, 4 Number of Core layer LocationThickness ( um ) Core Cu29 Build up Cu15 Insulation layer34 Solder Resist layer24 Core substrate800 Nickel plating Gold plating ( Immersion Gold) 3~7 0.03~0.12 Layer Structure Substrate Structure Core layer Ni Plating Au Plating Build up layer Solder resist Ni Plating Au Plating Build up layer Solder resist Solder Layer Number

11 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. Chip Capacitor Rule C A B G UNIT: um 0402 Pad ABC G (min) Pad ABC G (min) Pad ABC G (min) Pad ABC G (min) 750 Assembly Rule

12 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. C D B A E Peripheral bump allocationArray bump allocation F Notes: * If it is array bump placement for Over molded FC CSP, there is a limitation for no bumps by 2x2mm area in the center of die. Die Unit : mm ** The bump pitch 315 um min. should be regarded with substrate C4 pads design. For routing concern, the design of bump pitch should be larger than 315 um for layout routing. FC CSP Over molded FC CSPUnderfilled FC CSP 4 ≦ A, B ≦ 15 A Package size C ≦ (A-2) D Die size ≦ (A-3) E Bump pitch 0.25 min. By peripheral for substrate design F Bump pitch0.25 min. By array for substrate design RemarkItemDesicription Dimension 4 ≦ A, B ≦ 15 14x22 is Max. rectangular package size B ≦ (B-2) ≦ (B-3)

13 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. 13 Die on the top A B G1 H1 G2 H2 A B G H Chip Capacitor Attached Area. Die on the bottom FCBGA

14 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. 14 Chip Capacitor Attached Area. B F E D C A A B F E D C Stiffener Ring Once-piece Metal Two-piece Metal HFC BGA Two-piece Metal One-piece Metal

15 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. 15 MCM / FCBGA Chip Cap Attached Area. G1 H G2 G3G4 A A1 B1 F A2 B2 Cx1 Dy1 Dx1 Cy1 Cx3 Dy3 Dx3 Cy3 Cx2 Dy2 Dx2 Cy2 E MCM / HFCBGA Multi-Chip Module

16 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. 1. Fiducial Mark Of Flip Chip Process (exposed size) Unit : um TYP.SPECIAL (min) A Distance between die edge corner to the center of fiducial mark for adding spreader Could be even smaller if there is No heat spreader requirement B Diameter of Circle Mark If there were SMD component, Special rule can’t apply. C Width of square mark If there were SMD component, Special rule can’t apply. D Length of square mark If there were SMD component, Special rule can’t apply. ● Fiducial mark should be put on the outer side's of die edge corner 3 mm min. ● All the fiducial marks should be put on the diagonal location, and there must be two different fiducial mark on the diagonal location. Notes: ● Each substrate should have more than two fiducial marks for flip chip process. FIGUREDESCRIPTION SPEC REMARK B B C D A Fiducial Mark Rule - 1

17 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. 2. Solder Mask Opening for fiducial mark Unit : um TYP.SPECIAL (min) A Distance of S/M to fiducial mark 50-- B Distance of S/M to fiducial mark 50-- C Distance of S/M to fiducial mark 50-- A Distance of S/M to fiducial mark 50-- B Distance of S/M to fiducial mark 50-- C Distance of S/M to fiducial mark 50-- FIGUREDESCRIPTION SPEC. REMARK A Solder mask opening A C B For NSMD type C4 Pad For SMD (with solder) type C4 Pad C B Fiducial Mark Rule - 2

18 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. New Via Structure Time Line-I

19 ASE ADVANCED SEMICONDUCTOR ENGINEERING, INC. New Via Structure Time Line-II


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