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Power Integrity Analysis and Optimization in the Substrate Design Harini M, Zakir H, Sukumar M.

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Presentation on theme: "Power Integrity Analysis and Optimization in the Substrate Design Harini M, Zakir H, Sukumar M."— Presentation transcript:

1 Power Integrity Analysis and Optimization in the Substrate Design Harini M, Zakir H, Sukumar M

2 ABOUT CALIBER Caliber is a fast growing technology services company. Expertise is High speed PCB, IC package design. Highly proficient in Signal Integrity, Power Integrity, EMI/EMC analysis. Specializes in Embedded design services, ATE hardware & Thermal analysis. 120+ highly skilled design engineers. High quality & timely deliverable with attractive cost. Highest customer satisfaction.

3 SERVICES Pre layout & Post layout Serial & parallel interface (DDR 2/3/4, gigabit-SERDES) Co-design (IC/package/board) IBIS/IBIS-AMI based system SI Crosstalk, channel loss, s-parameter, eye-diagram, timing analysis Signal Integrity DC Analysis (IR drop, voltage/current distribution, density plots) AC Analysis ( PDN impedance analysis, target impedance optimization, Transient noise estimation) Decoupling cap analysis & optimization Power Integrity EMI Radiation EMI Susceptibility Compliances to various EMI standards during design phase EMI/EMC Cadence Sigrity PowerDC, PowerSI, optimize PI Other EDA tools Simulation Tools

4 NEED FOR P OWER I NTEGRITY A NALYSIS ? Modern devices needs higher functionality at lowers possible power => Lower supply voltage Silicon density doubles every year => increase in core frequency => transient current requirement is getting higher at lower power supply voltages DC analysis (Cadence Sigrity PowerDC) AC analysis (Cadence Sigrity PowerSI) Decoupling cap optimization (Optimize PI)

5 SUBSTRATE DESIGN ATE TEST BOARD (silicon wafer testing) It is a multi layer PCB mounted to the ATE (Automatic Test Equipment) on which the device to be tested is placed. Probe Card Probe cards are test boards used to test and measure the IC before packing. It is a testing tool that delivers electrical signals to chips on a wafer by contacting the probes which is fixed on PCB with epoxy. It is an essential inspection device that enables a wafer to be tested by contacting each signal of the tester and pad on wafer with chip unit at the same time. Probe card types : 1. Epoxy Cantilever Probe Card 2. Cobra Vertical Probe Card

6 SUBSTRATE DESIGN Substrate A substrate is a base material that supports a microelectronic device. It is used in Vertical probe cards as interface between probe card and the wafer. Substrates are called as Vertical space transformers. A space transformer is a major component of a probe card. It provides pitch reduction, high routing density and localized mid-frequency decoupling. Types of Substrate : Depending on the type of material used, Design and Manufacturing process, the substrates are differentiated as 1. MLO (Multi Layer Organic) 2. MLC (Multi Layer Ceramic) MLC uses ceramic layers that exceed more than 20 layers whereas MLO has organic buildup on both sides of a core.

7 DC ANALYSIS OPTIMIZATION Systematic variation of various parameters and show impact of each of them. Changing the plane layer material (copper -> silver) Increasing trace width in the fanout layer to reduce DC drop. Increasing plane area (adding 1 or 2 extra power plane in ceramic layer) Increase via connectivity Increasing the plane thickness

8 DESIGN #1 24 layer stackup 1-DUT MLC substrate Total die pin count 936 pin Total thickness 2.8mm +/- 0.05mm

9 P OWER DOMAINS IR Drop target for S0_VDD < +/- 1%

10 IR DROP ANALYSIS ORIGINAL CASE : with 1 power plane in ceramic layer, copper conductor of 10 um thickness for power planes

11 CASE1 : ORIGINAL CASE + conductor material changed to silver => Change of material makes only 0.1% difference

12 CASE2 – CASE 1 + thin film layer fanout trace width is increased from 30 um to 90/100 um => Fanout trace width increase made significant difference

13 Hotspot region shown in the thin film layer

14 CASE3 - CASE 2 + 2 power plane in ceramic layer of 10 um thickness => Adding additional plane didn’t help much CASE3.1 - CASE 3 + improved via connectivity => Improving via connectivity made little difference

15 Improved via connectivity => Improving via connectivity make some difference

16 CASE4 – CASE3 + power plane in ceramic layer of 18 um thickness => Now we achieved the target

17 D ESIGN #2 33 layer 3-DUT 1623 pins/site Thickness 3.8mm +/- 0.05mm Similar trends were observed during IR drop optimization process

18 R ESULTS Similar trends were observed during IR drop optimization process

19 Z11 ANALYSIS Case#1: Original layout Case#2: Adding 1 power plane Case#3: Adding 2 power plane Case#4: Adding extra decoupling capacitors

20 Original Case#1 Case#2

21 Case#3 Case#4

22 Decap report for the best scheme

23 CONCLUSIONS Each layout should be seen on case by case basis for AC and DC analysis. Effectiveness of universal rule does not apply. Systematic analysis was done for DC analysis and AC analysis using Cadence Sigrity tool Bottleneck is to be found for each new layout for improving IR drop and meeting the target Z. Increasing fanout trace width and plane layer thickness was found to be most effective in these cases for improving IR drop Cadence Sigrity tools are very significant tools for doing such kind of analysis quick and efficient.

24 THANK YOU Contact us No.362,12th main road, Hosur Sarjapur Road, Sector-5,HSR Layout, Bangalore – 560 103, Karnataka, India Direct line: +91 82200 45099 Visit us at

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