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Challenges With Package on Package (PoP) Technology

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Presentation on theme: "Challenges With Package on Package (PoP) Technology"— Presentation transcript:

1 Challenges With Package on Package (PoP) Technology
Greg Caswell Sr. Member of the Technical Staff CTEA meeting 21 February 2012

2 Agenda Root Cause PoP Background Next Generation PoP
Through Mold Via PoP Background Configurations and Examples PoP compared to SiP Assembly Warpage Issues Drop Testing Impact Thermal Cycles Reliability Underfill

3 Benefits of PoP The benefits of PoP are well known. They include
Less board real estate Better performance (shorter communication paths between the micro and memory) Lower junction temperatures (at least compared to stacked die) Greater control over the supply chain (opportunity to upgrade memory and multiple vendors) Easier to debug and perform F/A (again, compared to stacked die or multi-chip module or system in package) Ownership is clearly defined: Bottom package is the logic manufacturer, the top package is the memory manufacturer, and the two connections (at least for one-pass) are the OEM

4 Package on Package (PoP)
A configuration where two packaged integrated circuits are placed directly on top of each other Can also be known as stacked packages Interconnects are between the top package and the bottom package and the bottom and the PCB Top package traditionally contains multiple or stacked die Bottom package traditionally contains smaller / thinner die

5 PoP (Stacked BGAs) Bottom Package Top Package
Has land pads on top perimeter to allow for top PoP attach Molded using special process to keep perimeter clear Requires thin die and mold cap to allow for top package clearance Top Package Based on conventional stacked die BGA but larger ball size and thinner mold body Ball pitch and size constrained by need to clear bottom package Packages must be capable of being placed on the printed circuit board (PCB) and reflowed simultaneously to each other and to the board

6 PoP Stacked BGAs (cont.)
Both packages are relatively thin Maximum height typically 1.4 to 1.6 mm Focus tends to be on slimming top package Thinning of bottom package can be difficult Thinner substrate can increase warpage Smaller ball size can impact drop testing and temp cycle Standard package sizes 15x15 mm, with 14x14 and 12x12 also available 0.65mm pitch, with 0.5mm and 0.4mm available Ball size can vary from 0.45 to 0.35mm

7 PoP Examples Stacked Package on Package (PoP): The placement is often arranged through a soldering operation, but can also be performed with other interconnect technology Example of package on package device from Samsung Example of package on package devices, with stacked die in each package, from Mitsubishi 7

8 PoP Examples (cont.) Texas Instruments

9 Why PoP? Yield / Flexibility / Ownership
No issues with known good die (KGD) Memory can be easily upgraded Also allows for multiple sourcing Ownership is clearly defined Bottom package: Logic manuf. Top package: Memory manuf. Board level connection: OEM

10 Thermal Comparison 10

11 PoP Uses Dominant use Integration of digital logic device in bottom package with combination memory devices (i.e. DRAM and flash) in top package Top package typically stacked die Some pure memory PoP solutions also available Cameras / mobile devices are main users Increasing interest from high rel industries 11

12 PoP Assembly Process Assembly of PoP can be through one or two reflows
Most commonly single reflow (aka, one-pass) Top package is typically dipped before placement Flux (sticky) or solder paste

13 PoP Assembly (cont.) PoP can also be offered as a two-pass assembly
IDM assembles top and bottom package and places them in a carrier for board- level assembly Other assembly options include use of solder on pad (SoP) on bottom package

14 Solder on Pad (SoP) Consists of solder balls on the topside of the bottom package Designed to induce a larger solder joint collapse to absorb package warpage Difficulties Balls must be well aligned (limited self-alignment) Top package can slide off the balls during placement or reflow, leading to a poor solder joint or bridging

15 Design Factors Impacting Warpage
Mold Material property Shrinkage Thickness Die Die size Die Thickness Die attach Material property Thickness Laminate Substrate Properties Thickness Cu ratio Routing

16 Warpage Many technical challenges present in PoP assembly
Improper reflow profiles can lead to solder balls dislodging or migrating off the pad Excessive warpage can lead to solder ball bridging, solder slumping, head and pillow defects, or open joints Number one challenge in assembly is controlling and matching warpage of top and bottom packages More than 90% of the defects in PoP assembly are due to package warpage (cit. KIC) Minimizing warpage is a trade off between materials, temperature control and time The extent and degree of warpage is increasing as substrates become thinner

17 Package Warpage Due to mismatch in CTE between the substrate, mold compound and die Die attach can also play a role High Tg mold compounds are used to balance CTE mismatch between die and substrate Effect of mold compound becomes negligible at reflow temperatures

18 Warpage (cont.) General warpage trend at room temp. Inconclusive
Some claim bottom is smiling (positive, concave) while top is crying (negative, convex) Others claim the reverse Partially dependent if CTE of mold compound is more / less than substrate Example: Periphery of bottom package is devoid of mold compound At reflow temperature, exposed substrate could expand more compared to substrate under the mold compound Desirable to have matching warpage

19 Warpage and Yields

20 Warpage Drivers: Die Thinner die and smaller die tend to minimize warpage Larger / thicker die tend to drive crying at RT

21 Warpage and Reflow Profile
Ramkumar, 2008 European Electronic Assembly Reliability Summit

22 Reliability: Drop Testing / Warpage
Each board was dropped 200 times per JEDEC JESD11-B22 1500g for 0.5ms The bottom package was always first to fail Inline with other studies No significant differences in top package reliability Reliability seemed to be independent of yields and warpage

23 Reliability: Drop Testing / Warpage
Test vehicle was a mechanical dummy of a cell phone The drop-test was 3 cycles on six sides = 18 drops from 1.5m Process Development and Reliability Evaluation for Inline Package-on-Package (PoP) Assembly (Flextronics)

24 Drop Testing / Warpage (cont.)
Four different failure modes observed during drop testing Failure mode 4 was only found on combination B Combination B Low yield with ENIG surface finish Poor warpage alignment

25 Underfill Typically a filled epoxy High modulus (>10 GPa)
Range of coefficient of thermal expansion (CTE) values (16ppm – 30ppm) Improves drop test performance Reduces stress on interconnect due to substrate bending Improves thermal cycling robustness Reduce shear stress on solder Links die and substrate to reduce thermal expansion mismatch

26 Underfill Design Considerations
Design Considerations for Package on Package Underfill In PoP, the top and bottom packages are usually the same size. Both levels must be underfilled for good reliability. They also must be filled simultaneously. The top layer underfills more slowly than the bottom layer because of the thermal delta between the top and bottom levels. In order to underfill both levels simultaneously, the fluid must reach the top of the second level gap.

27 Reliability: Underfill and Thermal Cycling
Temp cycle

28 Underfill and Thermal Cycling (cont.)

29 Underfill and Temperature Cycling
Rapid time to failure for underfills D / F / G Best reliability No underfill or underfill with Tg > 110C (A and C)

30 Reliability Underfill is increasingly being considered for PoP
Improves 2nd level reliability under drop testing However, increasing indications that use of underfill may greatly reduce reliability under temperature cycling Case Study (-40 to 125C) With underfill: 300 cycles Without underfill: >1000 cycles

31 Warpage Resolution High Density PoP (Package-on-Package) and Package Stacking Development Ways around package warpage Solder on pad (SOP) While previous PoP BLR investigations showed a tendency to failure at the bottom joints we see that the finer pitch resulted in numerous failures on the top joints early in the testing in leg 3. For this reason a better composition of top package ball and bottom package SOP was selected in leg4 which improved the BLR reliability

32 Next Gen PoP: Increased - Integration, Miniaturization, Performance & Collaboration
Signal processing µP integration Bband + applications - increased pin counts µP core speed 2 – 3X w/ each node 45nm) Transition to FC accelerates from 65nm Memory Interface Higher speed memory interface SDRAM – DDR –> LP DDR2 Wider memory bus 16 – 32 Shared to split bus to (2 channel) architectures Increased pin counts with size reduction requires 0.4mm pitch top and bottom Warpage control with thinner / higher density PoP stacks Signal integrity optimization, decoupling cap integration Power efficiency and thermal mngmt Si / pkg co-design for PoP to optimize for cost / performance Device Packaging System Dynamics Dynamics Challenges SCSP started as FLASH plus DRAM stack. Now most application include one or more logic device. Most cellular baseband IC suppliers are adopting POP as a means to: OEMS increase flexibility of memory supply by dual sourcing and configuring memory at the final assembly stage Increase total device yield and total cost since logic and memory packages are tested independently (significant at 3 or more die in a stack) IDMs can avoid dilution of margins resulting from memory device procurement Digital baseband will convert to flip-chip by 2006 TAPP will be adopted on the low end of the baseband market for size and cost reduction for single chip baseband packages POP with Interposer allows the customer to use a memory CSP with a full array of BGA balls Chip in substrate will allow smallest form factor for POP 400 65nm 400mW 64mm² Processor I/O CMOS Node Peak Power Ave. Die Size 600 45nm 800mW 50mm² 800 28nm 1.2 W 2008 2010 2012

33 Thru Mold Via Technology (TMV®)
Enabling technology for next generation PoP reqmts Improves warpage control and PoP thickness reduction TMV removes bottlenecks for fine pitch memory interfaces Increases die to package size ratio (30%) Improves fine pitch board level reliability Supports Wirebond, FC, stacked die and passive integration

34 Construction and package stack-up for the TMV PoP
Test Vehicle reported at SMTAI 2008 Reference : "Surface Mount Assembly and Board Level Reliability for High Density PoP (Package on Package) Utilizing Through Mold Via Interconnect Technology - Joint Amkor and Sony Ericsson", Paper

35 Viking RAMStack

36 Summary 390million PoP components shipped in 2010 up from < 5 million in Forecasted to grow at same high rate as Smartphones DDR2 2 channel and other new memory architectures driving higher density PoP memory interfaces Amkor pioneered 1st Generation PoP (PSvfBGA) and now leading in Next Gen high density PoP with TMV® technology shipping in HVM One pass SMT PoP stacking enables optimization of supply / logistics and lowest total cost of ownership Amkor and Universal Instruments planning 14mm 620 / 200 TMV PoP SMT stacking study and industry report to facilitate SMT yield / quality optimization

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