1. Advanced IC Packaging A Technology Overview…
July J. Park
C. Moll

2. A Chip is Useless w/out a Package
Delivers power to the Chip
Transfers information into and out of the Chip to the PCB
Draws heat away from the Chip
Protects the Chip from outside elements

3. IC Package Types (Lead Frame)
PQFP- Plastic Quad Flat Pack
Up to 304 pins (500 micron pitch)
Inexpensive (~ a penny per pin)
Hermetic (Good for Harsh Environments)
Smaller ASICs and lower performance, lower pin count Microprocessors.
TSOP- Thin Small Outline Package (TQFP- Thin QFP)
Very Low Profile
Common for Memory
Can Support Stacked Die
Can Support Flip chip
PLCC, SOIC, MLF, DIP, SIP, etc-
Smaller Pin Count (4-84 pins)
ALL Use mechanical based tools for design (AutoCAD)
NOT a Good Fit For APD
75% of IC’s are in Lead Frame Packages

4. IC Package Types Continued…
BGA- Ball Grid Array
PBGA (Plastic BGA)
Routable Laminate Substrate (Many Layers)
High Pin Count (Over 2000 pins)
ASICs, DSPs, PC Chipsets
Wirebond, TAB or Flip-Chip (Build-Up) attach
Build-Up Technology Requires Special Via Structures
Can support Via in Balls (uncommon)

5. BGA Continued… BGA- Ball Grid Array CBGA (Ceramic BGA)
LTCC- Low Temp Co-Fired Ceramic
MLC- Multi Layer Ceramic
Good Thermal and Electrical properties
Usually Flip-Chip and SiP (MCM)
Supports Smaller Feature Sizes (Interconnect Density)
Supports Via in Ball
Support for Die Cavities
More Expensive, Reliability Questions

6. BGA Continued… BGA- Ball Grid Array TBGA (Tape BGA)
1 Or 2 Layer Tape (Usually 1)
CSP- Chip Scale Packaging
Very Low Profile
Good Thermal and Electrical Performance (Short Vias)
Smaller Pin Count
Cavity Down

7. Die (Electrical) Attachment
Wire Bond
Tape (TAB)
Flip-Chip (C4)
Direct Connect (Bumpless Build-up)
Chip On Board (COB)
FCOB (Flip-COB)

8. Wirebond Attachment Used in Lead Frame, PGA and BGA packaging
Over 80% of Packages are Wirebonded
Epoxy Glue to Attach Chip
Typically Gold Wire
Also Copper, Aluminum
Wire length- typ. 1-5 mm
Wire diam.- typ µm
Inexpensive, Reliable

9. TAB (Tape Automated Bonding)
Interconnect Patterned On Tape
Stronger Lead Bonding Strength
Supports Smaller On-chip Pin Size and Pitch
Supports up to 850 Pins
Better Electrical Performance than Wirebonds
Area TAB for Flip-Chip

10. Flip-Chip (C4) Attachment
What is Flip-Chip-
A method to electrically connect the die to the package carrier
The bond wire is replaced with a conductive “bump” placed directly on the die surface
Under-fill epoxy is used to secure the attachment and absorb stress
The chip is then “flipped” face down onto the package carrier using a re-flow process
Bump sizes range from microns in diameter
Also known as C4 (Controlled Collapsible Chip Connection)
Invented by IBM

11. Flip-Chip Continued Flip-Chip is NOT:
A Specific Substrate Material like LTCC or FR4
A Specific Package like SOIC
A Specific Package Type like QFP, BGA or PGA

12. Advantages of Flip-Chip
Reduced Signal Inductance
Shorter Interconnect Lengths
Use Power More Efficiently
Power Directly at the Core
Higher Interconnect Density
More Routable Area
Smaller Package Size
Chip Scale Packaging (CSP)
I/O Not Controlling Core Size
Area Array Placement
Possible Die Shrink

13. More about Flip-Chip Two methods of “Bumping” the Chip:
RDL- Re-Distribution Layer
Direct Bumping (UBM)

14. More Flip-Chip… Stud Bumping High Pin Count ASICs and Microprocessors
Direct Gold Bump Placed on Die Bond Pad
Supports Tighter Pin Pitch
High Pin Count ASICs and Microprocessors
Typical Package is CBGA or TBGA (> 600 pins)
Tape Carrier Package Used for < 600 pins

15. Flip-Chip…The Build-Up Process
Based on High Density, Micro Via Organic Substrate
Also Referred To As Sequential Build-up
Requires Flip-Chip Escape Route Patterns
Typical Package Assembly Based on a 2layer Core
and Build-Up From Each Side of Core
i.e. 3/2/3 process equals 3 build-up layers from each core side
Build-up is Less Expensive Than LTCC. However, LTCC Exhibits Better Die Shrink Support with Same Build-Up Arrangement (a 3/2/3 process)
Die Cost (size) Drives Use of Flip-Chip, Build-Up Process
2layer core

16. Flip-Chip…The Build-Up Process
Layer to Layer Connections Typically Use:
Micro-Vias of 100um or Less
Special Patterns (Stagger, Staircase, etc.)
Core Vias Larger Than Micro Vias
Lines and Spaces < 35um
Use of Mesh Planes for Fabrication Yields
IBM
Unique uvia Patterns
Core via vs. uvia

17. CSP- Chip Scale Packaging
Definition: A Package is Considered CSP when it is Less than 20% Larger than the Die.
Usually Flip-Chip Attachment
Flex Tape and Wirebond also possible
Common for Wireless Handsets and Handheld Electronics .
Stacked die support (S-CSP- Stacked CSP)
Laminate and Ceramic Substrates

18. 3D Packaging- Stacked Die
Definition: Packaging Technology with 2 or More DIE Stacked in a Single Package or Multiple Packages Stacked Together
Supports
Wirebond Die Attach
Flip chip Die Attach
Hybrid- Combination of Flip-Chip and Wirebond Attach
Packaging Applications
CSP (most common)
PBGA, BGA, TSOP, TQFP etc.
Benefits of 3D Packaging
Smaller, Thinner and Lighter Packages
Reduced Packaging Costs and Components
Reduced System Level Cost for System in Package (SiP) vs System on Chip (SoC) approach
System Level Size Reduction Due to Smaller Footprints and Decrease Component Count (SiP)
Common for Wireless Handsets, Handheld Electronics and Memory Intensive Requirements.

19. Hybrid (Thin & Thick Film)
Definition: A Single Substrate with Monolithic and Film Elements
Passive Circuit Elements Deposited on an Insulating Substrate
Usually Ceramic Substrates
Alumina, Beryillia, Aluminum Nitride
Conductors Usually Gold, Silver, Palladium and Platinum
Unique Design Requirements:
Paste/Ink Resistors (Laser Trimmed to .1%)
Dielectric Crossovers
Wire Bonding
Packaged in Sips and Dips (low pin count)
Medical, Aerospace, Automotive

20. SiP- System In Package (MCM)
Wireless (RF) Market is the Key Driver
Motorola, Philips, Conexant, etc
LTCC is the Substrate of Choice
CBGA Package
SiP is NOT SOC (System On Chip)

21. Advantages of SiP over SOC
RF IC’s Typically Take 3-5 Manufacturing Passes
Mask Sets Cost Up To One Million Dollars Each (130nm)
Total Cost of Up To 5 Million Dollars
6 Month Impact to Schedule
SiP on LTCC
Total Cost Less Than 500K for 3-5 Manufacturing Passes
6 Week Impact to Schedule
Mixed Technology Support
CMOS, GaAs, SiGe all on One Substrate
Flexible Design Partitioning
Bluetooth Standard Platform

22. Current RF Module Process
RFDE
Library (models)
ADS Sim
ADE
Composer Schematic Capture
Spectre (RF) Simulation
Binary
ADS
Schematic Capture
Virtuoso
IC Layout
Assura
Extraction/LVS
IFF
ADS
RF Layout
Momentum
2D Planer Solver
LEF/DEF
Parasitics/S Parameters/Spice
IFF
Gerber
Union
Design Entry HDL
Schematic Capture
Pst Files
APD 610
SiP/Module Layout
This is a commonly used flow for RF Module (SiP) Design. The schematic for the RF IC is Captured in Composer and Simulated in ADE (formally know as Analog Artist) with the Spectre and Spectre RF simulators. Through the Agilent partnership additional models and simulation capabilities are integrated into Composer and the DFII environment. This is bundled in a product available directly from Agilent called RFDE (Radio Freq Design Env). The Composer schematic directly feeds into Virtuoso for IC layout. Assura RCX is integrated into the flow to extract parasitics from the IC layout and for LVS. This helps to keep the logical and physical data in-sync with each other. In June of 2003 the Agilent partnership will integrate Momentum (2D Planer Field Solver) into Virtuoso for advanced parasitic extraction from the IC layout. The Top Level pin information from Virtuoso will be used to generate the IC footprint for the Module. This is done through the LEF/DEF interface in APD. The Module level schematic can be entered in Agilent ADS and/or in Concept HDL. IFF is the file format that can be used to transfer the ADS schematic into Concept. Small Sections of the Physical design can be done in ADS layout and passed into APD through the IFF interface. The complete Module is assembled in APD and Manufacturing outputs can be created. APE can be used for Extraction and Simulation of the Module level interconnect. Through Ansoft Links, HFSS can be linked to the flow for S Parameter extraction, etc.
APSI 620
Module Level Analysis
Cadence
Ansoft Links
Agilent
Ansoft HFSS
3D Extraction
Ansoft

23. RF SiP Requirements Schematic Driven Buried Discrete Components
Mostly Inductors (Spiral) and Capacitors
Parameterized Elements
Component Level LVS

24. Current Trends 3D Packaging- Stacked Die Build-Up Substrates Flip-Chip
DCA- Direct Chip Attach (Bump-Less)
SiP
LTCC, Bluetooth Standard
“Green” Manufacturing
Removing Lead (Pb)
New Materials (tin, silver, copper) for Die Attach, plating, solder balls
Standard Packages
Custom Packages Too Expensive

25. Who’s Who in IC Packaging
In 2004 STATS merged with ChipPAC to become #3