1. Packaging workshop Main Discussion points & List of Actions Packaging Workshop Berlin, 23/11/2010

2. Main discussion points  Embedding technologies for module manufacturing (TUB)  For thin chips up to 50µm, a RCC (resin coated copper) is used up to 90-100µm.  For thicker chips or components, prepregs (resin+fiber) with cavities around the component and a cap prepreg on top are used for embedding.  Chip pad requirements for face-up: >85µm, Cu metallization on Al: 5-7µm thick (by electroplating).  For face-up chip assembly: 20µm DAF (die attach film, non conducitve) or 20µm solder/silver adhesive for power chip applications (enhanced thermal dissipation from chip backside).  For <80µm resin thickness, laser blind µvias to Cu pads are possible and therefore face-up approach can be followed. The smallest laser µvia that has been opened is 30µm. An aspect ratio >1 (resin thickness/µvia diameter) has to be hold for successful copper electroplating of the µvia.  For >80µm resin thickness, only mechanically through vias can be opened.  The RCC or prepreg is laminated under 20 bar pressure and cured at 185°C-190°C. More info in TUB presentation.  If only chips with Al pads are available, then TUB/IZM can deposit 30µm thick Gold stud bumps and subsequently assembled in a „flip chip“ fashion. This can be the choice for some chips in the beginning of WiserBAN project.

3. Main discussion points (Cont.)  Module prototyping & configuration scenarios for WiserBAN packaging platform  The routing in the embedded module will lead to top and bottom inteconnection pads >200µm with a pitch >200µm.  Pad size should be at least 200µm due to interconnectivity issues using ACAs (Anisotropic conductive adhesives) by module stacking.  State-of-the-art copper structuring at module level lies at 50µm L/S (line/spacing) with 16-20µm thick Cu using subtractive technology and lately very fine structuring at 15µm L/S with 10-12µm Cu by semi- additive technology.  Stackability of modules is a new R&D thema for TUB/IZM. R&D will focus on ACA, ACF (anisot.cond.film), ICA+NCA (isotropic and non conductive adhesives), ESP (encapsulated solder particles) etc.  For thicker chips or components, prepregs (resin+fiber) with cavities around the component and a cap prepreg on top are used for embedding.  Concern is raised about the survivability of the encapsulated piezo-MEMS under 20 bar lamination pressure. The lid and kind of stiffener can help MEMS stand to high pressure. MEMS with 300µm thickness will be embedded and experimental results will be evaluated. These MEMS will be provided by EPCOS.

4.  Module prototyping & configuration scenarios for WiserBAN packaging platform (Cont.)  LETI (Carolynn) may be able to provide about (8) BAW MEMS with Al pads. Chips are 250µm thick. TUB will do Au-stud bumping and the chips will be assembled like flip chips. The 30µm Au bumps may protect sufficiently the 15µm membrane provided that collapse during assembly can be well controlled. (Action point)  Pad size should be at least 200µm due to interconnectivity issues using ACAs (Anisotropic conductive adhesives) by module stacking.  Platform Scenario 1: RFSoC layer, piezo layer, antenna +IPD in separate modules forming a subsystem platform and subsequently the subsystem together with EEPROM and power supply assembled on PCB.  Platform Scenario 2: Later in the project, the RFSoC layer with piezo can be integrated in one module with antenna either as another module on top or as separate 50  connection on the board together with EEPROM and power supply. This scenario leads to thinner build-up and it really depends on end- user miniaturization requirements (e.g Medel requires <1mm thick platform build-up). WiserBAN will go at the end for 4mmx4mmx1mm module.  The plan is to keep scenario 2 adjustable to end-user desirable build-up, having only fixed a generic “RFSoC+piezo” subsystem module. The posititioning of the antenna should be still discussed. A conceptual design would be: o For Medel+ Sorin (implantable): the “antenna+IPD” on substrate plus the generic “RFSoC+piezo” module. o For Siemens+ Debiotech: the “antenna+IPD” as a module on top of the generic “piezo+RFSoC” module.  TUB in task 5.1 prefers to start with “Scenario 1” in order to build separate modules and start investigating module stackability with dummy or functional modules. Main discussion points (Cont.)

5.  EPCOS MEMS packaging & Candidate packages for WiserBAN  Evolution of CSSP packaging (For BAW and SAW filters) (CSSPlus and CSSP3 Cu-frame) (See EPCOS presentation)  CSSP3 Cu-frame is the smallest package (1.4mmx1.1mmx 0.450mm) (For BAW or SAW chips) (HTCC:200µm, chip:130µm). The smallest version could be 1mmx1mm. Ni/Au metallisation on CSSP3 Cu-frame (Ni>5µm, Au ~100nm).  New DSSP packaging for SAW filters. A smallest package (0.8mmx0.5mmx 230µm w/o bumps) could emerge in near future. It would be very attractive to use it in WiserBAN. CuNi interconnect (9µm Cu/3µm Ni by electroplating)  An alternate narrowband SAW targeting the new Medical Implant at 2.4835-2.5GHz would be interesting as alternative (i.e. similar interface characteristics).  VTT antenna and silicon resonator  Silicon resonator: 1mmx1mmx230µm (See VTT presentation). Explore 2 scenarios: o First: The VTT resonator can be alternatively packaged in CSSP format by EPCOS o Second: or it will be embedded as a package developed by VTT & IZM  IPD: Quartz substrate with possible high-resistive silicon alternative (See VTT presentation). o 1-metal layer approach: Metal copper 5±2µm thickness o 2-metal layer approach: 2x10µm thick copper + 20µm BCB interposer o external: 1-turn inductor on quartz of ~100 quality factor, 4-turns inductor on Quartz with ~75 quality factor.  The substrate side with the antenna (=>metal) cannot be placed on the PCB side without killing the radiation performances: how can the interconnection be realised?  A separate meeting may be needed for the IPD layer integration.

6. Main discussion points (Cont.)  Sorin:RF implanted medical application example  System: Antenna+Antenna matching network+Crystal oscillator+SAW filter+RF transceiver (See Sorin presentation)  All targered components have to be „medical graded“. The Coilcraft and Vishay components are certified; are the other components compatible?  Based on used ZL70101 (Zarlink), the voltage range is 2.1-3V, the interface is a standard 4-wires SPI. The attenuation at 405MHz is 35dB.  CSEM will provide a specification template for each end-user scenario in order to have common specification points, especially regarding the hardware (SoC). (Action point/CSEM)  Medel: Cochlear application  Existing design: LTCC substrate+ passives+antenna  Voltage: 2.7V-6.8V  Volume: 40mmx20mmx3mm. The target is to thin it down to 1mm.  Current consumption: 1.2mA, 3V.  Battery should be recharged once/day.

7. Action points  LETI will check if a number (8?) of dies&lattice BAW filters can be sent to TUB for gold stud bumping and assembly. Also as reminder, LETI will check the availability of ST Microel. functional chips from multiproject wafers. (Action LETI/Carolynn)  EPCOS to provide BAW filters in CSSP3 format. Is it possible instead of Ni/Au to have Cu finish? (Action EPCOS/Jean-Michel)  EPCOS to examine if DSSP package for SAW filter can come without solder balls. Can it also come only with Cu metallisation? Supply Cu/Ni thickness for DSSP. (Action EPCOS/Jean-Michel) (Done)  TUB will ask Murata for thin capacitors and inductors with Cu terminals (Action TUB/Dion)  Medel will provide information to TUB for capacitors and inductors with Ni/Pd metallisation (Action Medel/Josef)  CSEM will try to find some RF SoC chips available in other projects (Action CSEM/Erwan/David)  CSEM will provide a specification template for each end-user scenario in order to have common specification points, especially regarding the hardware (SoC). (Action point/CSEM/Erwan)  Organise a technology exchange meeting for antenna & IPD (Action VTT/CSEM) (Pradeep/Jouko/Erwan)  All available components found from the above actions will be used by TUB to build the first modules (even dummies) and subsequently develop module stacking processes. (Action TUB/Dion)