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Next Generation System in a Package Manufacturing

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Presentation on theme: "Next Generation System in a Package Manufacturing"— Presentation transcript:

1 Next Generation System in a Package Manufacturing
Lars Böttcher Fraunhofer IZM Berlin

2 Outline Introduction to Chip Embedding Technology HERMES Project
Process overview QFN Package realization Ultra fine line Ultra Fine pitch Applications Conclusions

3 Interconnect Evolution
µVias LDI Embedding HDI PCBs technology challenge / potential Flip Chip progress of organic substrates enabled advance in interconnect technology chip & wire

4 Chip Embedding - Technology Progress
Chip Embedding in organic substrates  use of PCB technology & material Production started Korea Japan First Standard JPCA EU Companies ready First Patent Basic R&D Production Demos Production 1968 2000 2005 2010

5 Chip Embedding - Different Approaches
Chip Last / Pad Connection Chip First / Via Connection core assembly embedding use of pre-tested cores different interconnect technologies (wires, solder, adhesives) contact by micro vias chip assembly in PCB flow highest possible miniaturization pictures: Shibata, JPCA

6 Chip First Embedding - Process Alternatives
Face Up Face Down die placement embedding via formation plating & etch electrical and thermal backside contact better fine pitch capability

7 HERMES High Density Integration by Embedding Chips for Reduced Size Modules and Electronic Systems Please visit: for more information Project EU funded project, FP 7 program, Started: May 2008, Duration: 36 month Total budget (approx.): 16 M€ Project Goal Industrialization of the results of the HIDING DIES project Improvement of technology towards finer pitch, use of new material developments, process innovation and equipment improvements Strong focus on future implementing of the technology in a manufacturing environment / assembly chain Consortium 11 partner; technology provider, end-user, testing, research institutes Early Adopters Group with potential end-users

8 HERMES – Technology Development Roadmap
Industrialization Goals manufacturing panel size 18"x24" lines/spaces 25 µm, semi-additive technology die pitch 125 µm peripheral, 250 µm area array stacking of 2 levels with embedded chips Demonstrator Applications Power module for house hold (4 ICs, large power dissipation) Communication modem (> 10 ICs, high complexity) Motor control unit (high-end micro controllers) Secure phone module Advanced Technology Goals lines/spaces 15 µm, semi-additive technology die pitch 60 µm stacking of 2 levels with embedded chips

9 Outline Introduction to Chip Embedding Technology HERMES Project
Process overview QFN Package realization Ultra fine line Ultra Fine pitch Applications Conclusions

10 Process Flow Face-Up Embedding
Panel format 610 x 456 mm² 50 µm chips with 5 µm Cu or Ni/Pd pad metallization Die attach (Datacon evo/Siplace CA3) using 20 µm DDAF (dicing die attach film) Embedding (Lauffer) by RCC lamination (5 µm Cu, 90 µm dielectric) UV laser drilling (Siemens Microbeam) of microvias Cu electroplating / via filling Dry film resist application Laser Direct Imaging (Orbotech Paragon 9000) of circuitry pattern Subtractive Cu etching Lamination Via drilling Cu Plating Imaging Etching

11 Process Flow Face-Up Embedding
a) Die Bonding to substrate d) Copper metallization b) Vacuum lamination e) Patterning of circuitry c) Laser drilling of micro via

12 Embedded QFN Embedded die package test vehicles
QFN type  single package BGA type  stackable package size 10x10 mm² / thickness approx µm 84 I/Os, 400 µm pitch chip size 5x5 mm / chip pitch 100 µm Realized on panel size: 350x250 mm² QFN type BGA type

13 Embedded QFN – Process Wafer preparation
Chip preparation and Die Bond Wafer preparation Application of suitable pad metallization (Cu or Ni/Pd) Thinning to 50 µm and dicing Die bond material Application of DDAF prior to dicing Requirements handling of very thin chips (50 µm) very high placement accuracy essentially for following process steps Die bonded chips on copper substrate

14 Embedded QFN – Process Lamination
Dielectric lamination Lamination embedding of chips by vacuum lamination of RCC use of epoxy-based RCC optimized lamination profile to ensure void and damage free embedding of Si chips no chip movement during lamination process Chip Adhesive Substrate Epoxy x-section embedded Si chip

15 Embedded QFN – Process Laser drilling
Micro via formation Laser drilling pulsed UV laser, enabling ablation of metal and epoxy layers Development towards smaller via diameter needed: target 30 µm UV Laser drilled via, 30µm diameter

16 Improvement in desmear process
Embedded QFN – Process Desmear and Cu plating Strong increase of via diameter after desmear process by more than 50% Adaption of process parameters Defect free copper filling of micro via Improvement in desmear process Desmear + Copper plating

17 Embedded QFN – Process Fine Line copper structuring
Wiring structure sizes 50µm lines/space (subtractive): Use of laser direct imaging system with local alignment option 25µm thick DFR Acidic spray etching of structures Resist mask Etched wiring structure Etched wiring structure (detail)

18 Embedded QFN Test vehicle for: Reliability testing
Easy electrical testing Processing on large panel format overall thickness 160 µm standard QFN footprint Automated testing using QFN test board: daisy chain four point Detail

19 QFN Package reliability
Reliability testing Passed: preconditioning with MSL3 (192h, 30°C/60%RH) (JEDS E) Passed: TC (-55 ° C/125 ° C, 1000cycles), HTS (150 ° C, 1000h), THS (85 ° C/85%, 1000h) Delamination at resin/chip and DAF/chip at PCT (168h, 121C, 100%RH, 2 atm) PCT Resin/chip delamination PCT DAF/FR4 delamination

20 QFN Package reliability
Warpage No symmetrical lamination Improvement with 100µm FR4 Embedding resins with high Tg and fibers 50µm FR4 100µm FR4 Warpage reduction from 200µm to 20µm with increased substrate thickness

21 Ultra fine line development
Exposure by Laser Direct Imaging (LDI) Maskless processing capable of large substrate sizes 25µm thick dry film resist (DFR) Goal: 15 µm L/S pattern on PCB Reliable development of resist structures Resist removal Cu base etched

22 Ultra fine line development
Ultra fine line copper structuring Goal: 15 µm line/space Thin (2 µm) base copper foil Suitable dry film resist and substrate preparation (resin thickness & adhesion) Dry film resist removal Use of thin copper foils to enable reliable differential etch of initial Cu layer x-section 15 µm L/S after Cu plating x-section 15 µm L/S after differential etch

23 Ultra fine pitch development
Future Development  Via-less Embedding Cu lines are formed in direct contact to Cu bumps no drilled vias much less constraints in tolerances expectation 50 µm pitch under development

24 Outline Introduction to Chip Embedding Technology HERMES Project
Process overview QFN Package realization Ultra fine line Ultra Fine pitch Applications Conclusions

25 Where to use Embedding? many different components one / few components
Complex Systems Packages / System in Packages / Modules many different components  high risk in yield one / few components

26 Applicatio - Dual chip package
Two + two build up layer Package outline 15 x 15 mm² 120 µm Pad pitch Min. L/S: 50 µm Challenges Die bonding on both substrate sides High wiring complexity and density Multiple build up layer top chip bottom RCC 1 RCC 2 adhesive cross-section of dual chip SiP

27 Application - Dual chip package
System in Package BGA Module Two embedded Si chips of 50µm thickness Five Cu routing layers stacked micro vias Overall package thickness: 450µm JEDEC Level 2A passed 1000 cycles -55 / °C passed 1000 h 85 °C / 85 % r. h. passed cross-section of complete SiP

28 Application - Power Packages
Cooperation with Infineon Technologies Embedding offers a technology platform enabling a large variety of packages different package types realized reliability qualification passed advantages low inductances low resistance reduced cost SMD package with embedded MOSFET

29 Multi Chip Package Package containing two power IC and a logic IC
Challenge: Combination of required thick Cu metallization for power chip with fine pitch requirement of logic chip

30 Outline Introduction to Chip in Polymer - Embedding Technology
HERMES Project Technology Process overview QFN Package realization Ultra fine line Ultra Fine pitch Applications Conclusions

31 Conclusion Embedded Chip Technology
Next generation package realization by embedding of bare dies into laminate layers Industrialization of the technology within the “HERMES” project Realization of different packages: Single and multi die packages reliability comparison to conventional packages Further developments target: Ultra fine pitch chips with peripheral pad pitch down to 60 µm Ultra fine line development towards 15 µm lines/space using semi additive processing Wide range of laminate materials for embedding Transfer of technology to new process line, capable of substrate sizes up 610 x 456 mm²

32 Thank you very much for your attention!

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