1. DIGITAL SYSTEMS Sequential Logic Design November 28, 2004 Rudolf Tracht and A.J. Han Vinck

2. Types of logic: combinational memoryless combinational current inputOutput Output depends on input only

3. Types of logic: sequential Mealy machine Output depends on current input and memory content current inputOutput memoryless combinational memory For binary logic with n memory elements we have 2 n states The memory elements contain all the information about the past, necessary to account for the system‘s future behavior Combinational logic memory content changes every T seconds Not present for Moore machine clock

4. Clock ( active high ) change state time clock clock edge Example: Clock frequency = periods/second = 1 MHz (Herz)  clock period 1  Sec clock period T clock frequency 1/T T

5. Sequential: –input A, B –wait for clock edge –observe C –Input A, B –wait for another clock edge –observe C again: may be different B A Clock C

6. stability 2 examples Propagation delay Q Q‘ Bistable circuit 01 1 0 Q 1 Q‘ 1

7. Use the freedom to fix output R S Q T SR Q T 11 last Q last T 0101 1010 0011 from SR = 00 to SR = 11 gives unpredictable next state „state“ 00  01  11  Q = 0 00  10  11  Q = 1

8. Key idea! 1.avoid SR = 00 as input 2. force SR = 11 if output must be fixed ( use C = 0 ) D C RSRS DCRS 0110 1 1 01 0 0 1 1 1 0 1 1

9. Result is a sequential device: D-latch Used to „freeze“ information depending on control C D C Q Q‘ C D Q Q‘ D‘+C‘ D+C‘ 1 0 0 1 1 0 1 1 1 0 0 1 0 x last Q last Q‘ 1 1 D‘+C‘ D+C‘ data input control

10. Ideal Timing for a D-latch D C Q Follows D Stores D C D Q 1 0 0 1 1 1 0 x last Q Latch is not clock controlled:= asynchronous

11. sequential device: Flip-Flop Flip-flop –output changes at times determined by clock clock controlled:= synchronous

12. Edge-triggered D Flip Flop DDQ clk C D C‘ D CLK Q 0 1 X0last Q X1last Q C C‘ QM masterslave latch Ideal timing QM fixed Q=QMQ fixed take over

13. Cont‘d The edge of the clock is used to sample the "D" input & send it to „Q“ (positive edge triggering). –At all other times the output Q is independent of the input D –The input must be stable for a short time before the clock edge. C C‘ Q output fixed QM output fixed No change in D Q = QM C‘ QMQ C D master slave C‘

14. Edge-triggered D Flip Flop DDQ clk C D C‘ D CLK Q 0 1 X0last Q X1last Q D CLK QM Q QM masterslave latch Ideal timing

15. Cont‘d There are also –Negative-edge triggered D flip flops –Edge triggered J-K flip flops – 

16. J-K flip flop J K D clk Q

17. Edge triggered D and J-K flip flop D CLK Q Q‘ 0 0 1 1 1 0 X0last Qlast Q‘ X1last Qlast Q‘ J K CLK Q Q‘ 0 1 1 0 X X 0last Qlast Q‘ X X 1last Qlast Q‘ 0 0last Qlast Q‘ 1 1last Q‘last Q DJ-K

18. Application D flip-flop: Shift registers (delay line) Serial in, serial out Serial in serial out  Clock At each clock tick a new bit is shifted in. (This works only because every element has a certain delay and thus the input is taken before it changes)) After n ticks the bit appears at the output, is thus a delay by n clock ticks DQDQ QD D-flip-flop

19. Shift registers cont‘d Serial in, parallel out Serial in  Clock At each clock tick a new bit is shifted in Performs a serial to parallel conversion DQDQ QD D-FF

20. Parallel in Serial out parallel in clock sel Serial out FF

21. Parallel-in, parallel-out (2) D clk Q Load /shift Serial-in Q D D clk 1-in 2-in For serial operation

22. application Sampled speech: 8k samples/sec of 8 bit each –converted into serial stream of 64 kbit/s Computer serial output bus (e.g. RS-232) 0 1 data

23. Example unit delay: schematic representation x(t) u(t) = x(t-1) exclusive OR parallel-to-serial convertor P/S X(t-1)

24. R = ½ encoder u 1 (t) For every input bit we generate 2 output bits x(t-1)x(t-2) x(t) clock

25. State transition graph (1) 1/10 11 1/01 0/01 0/10 10 01 1/00 1/11 0/11 00 0/00

26. Trellis representation (2) 00000000 0000000000 11111111 010101 10101010 01 0101 11111110

27. Transition tables (3) input 0 1 Old stateoutput new state output new state 00 00001110 01 11000010 10 10010111 11 01011011

28. General finite state machine Specified by: inputs states transitions between states outputs connected to transitions Analyzed by: state transition graphs (Markov chains) state transition tables

29. State minimization Q: can we model with fewer states? are there states that do the same job? Definition: two states are equivalent if and only if, for any input of length k, k > 0, they give rise to the same output.

30. Algorithm for minimizing the state table Let S be the set of |S| states Step 1: divide S into groups of states with the same outputs given the inputs. If |S| groups remain, STOP Step 2: subdivide every group into subgroups that contain all states that have their transitions to the same groups created in the previous step If no group is further subdivided, STOP otherwise go to step 2. STOP: uniquely label every remaining group (equivalence class)

31. example input 0 10 1 old new state state output 1230 1 21 5 10 35801 45711 56210 65101 74711 82601 Step 1: Group together states with same outputs (1,3,6,8) (2,4,5,7) Step 2: form subgroups (1,3,6,8) (2,5) (4,7) (1,3,6,8) (2,5) (4) (7) STOP: 4 Representants: 1, 2, 4, 7

32. General realization Combinational circuit that realizes Output = f(input, old state) new state = h(input, old state) N inputs M outputs  D D D r digits new state r digits old state

33. Sequence delay operator transform a = a 0 a 1,..., a k,0,0,0,… A(X) = a 0 +a 1 X +...+a k X k Y(X) = A(X)*G(X) A(X) Application: shift register response with binary input and binary output. G(X) = 1 + X + X 2, where X is called the delay operator A(X) XA(X)X 2 A(X) clock

34. G(X) *A(X) 1a 0 a 1,..., a k Xa 0 a 1,..., a k X 2 a 0 a 1,..., a k-1 a k 1 a 0 + a 1 X + a 2 X 2,..., a k X k X a 0 X + a 1 X 2,..., a k X k+1 X 2 a 0 X 2 + a 1 X 3,..., a k X k+2 + +

35. Periodic sequences For a periodic sequence: A(X) = ( a 0 +a 1 X +...+a k-1 X k-1 ) (1 + X k + X 2k + X 3k +... ) = ( a 0 +a 1 X +...+a k-1 X k-1 ) / (1 – X k ) Note 1: (1 – X k ) (1 + X k + X 2k + X 3k +... ) = 1 Note 2: When we do calculations modulo-2, the – and + sign have the same effect.

36. Feedback shift register A binary linear feedback shift register 2 delay elements or flip-flops (we do not draw the clock anymore) output Homework: –what is in general the maximum period of the output –Calculate the output sequence XOR or modulo 2 calculations 10

37. Design Step 0: proper problem description Step 1: construct –state transition diagram –state transition table Step 2: choose flip-flop type for state memory Step 3: derive logic equations from table for Next state Output

38. Example: parity checker Problem: determine parity of 8-bits serially State diagram: 8 bits serial in Parity = 0 if even # of ones out Parity = 1 if odd # of ones Parity checker out = 0 out=1 in=0 in=1 in=0 in=1

39. tables in 0 1 0 1 old state new state output Even Even Odd 0 1 Odd Odd Even 1 0 in 0 1 0 1 old state new state output 0 0 1 0 1 1 1 0 1 0 Output = new state Next = out  in in out Old clock

40. CRC-Application Two standard polynomials called CRC-16 and CRC-CCITT are F(X) = 1 +X 2 + X 15 + X 16 CRC-16 F(X) = 1 + X 5 + X 12 + X 16 CRC-CCITT The CRC calculates X 16 A(X) modulo F(X) = subtract F(X) as often as possible from X 16 A(X), where A(X) = a 0 + a 1 X 2 + + a k-1 X k-1 ( and coefficient calculations done modulo-2) How do we implement this?

41. CRC-encoding The CRC encoder calculates { X 16 A(X) }modulo F(X) = subtract F(X) as often as possible from X 16 A(X), where A(X) = a 0 + a 1 X 2 + + a k-1 X k-1 ( and coefficient calculations done modulo-2) We transmit: – C(X) = [{X 16 A(X)} modulo F(X) + X 16 A(X)] = : [ CRC(X) +X 16 A(X) ] Note: Note: C(X) modulo F(X) = 0!

42. In communication context We receive: C(X)  E (X) We calculate: R(X) = {C(X)  E (X)} modulo F(X) –If R(X) = 0 no error (= assumption!) –If R(X)  0 error detected Note: all polynomials are binary and coefficient operations modulo-2 Theorem: For F(X) of the form 1 + + X n-k any error event of length  ( n-k ) gives R(X)  0

43. CRC cont‘d The following „clocked“ shift register can be used to implement CRC16: F(X) = 1 +X 2 + X 15 + X 16 Data in 13 flip-flops Example: X 16 modulo F(X) = 1 + X 2 + X 15 Question: When is the result A(X) mod F(X) equal to 0? What does this mean?

44. Cont‘d Example: calculate ( 1 +X 2 +X 4 +X 5 ) modulo ( 1 +X + X 3 ) –In binary: ( 1 0 1 0 1 1 ) modulo ( 1 1 0 1 ) The operations in binary are as follows 1 0 1 0 1 1 1 +X 2 +X 4 +X 5 0 0 1 1 0 1 X 2 ( 1 +X + X 3 ) 1 0 0 1 1 0 0 1 1 0 1 0X ( 1 +X + X 3 ) 1 1 1 1 0 0 1 1 0 1 0 0( 1 +X + X 3 ) RESULT: 0 0 1 0 0 0 X 2 Homework: draw the corresponding shift register

45. proof for an error event length  ( n-k ), E (X) has the form X*g(X), where g(X) has degree < (n-k) and thus E (X) cannot be a multiple of F(X). OK

46. Non-systemantic CRC Encode: C(X) = A(X) F(X) Receive: R(X) = C(X)  E(X) If R(X) modulo F(X) = 0 ( no error detected ! ) Decode: A‘(X) = R(X) / F(X) Otherwise declare error F(X) = 1 +X 2 + X 15 + X 16 A(X) 13 flip-flops A(X) F(X)

47. Examples of Polynomial * and / Assume all coefficient calculations modulo-2 and no clock drawn A(X) * G(X) G(X) = ? A(X) A(X) / F(X) F(X) = ? Homework: check this Homework: calculate the responses to A(X) = 1+X 2 +X 3. Can we combine G(X) and F(X) ?